coreboot-gerrit December 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/ironlake: Use `NUM_CHANNELS` macro
by 9elements QA (Code Review) 23 Dec '21

23 Dec '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60225 ) Change subject: nb/intel/ironlake: Use `NUM_CHANNELS` macro ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 7 / 1 / 8 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/85589 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/85588 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/85587 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/85586 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/85585 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/85584 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/85583 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/85582 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/60225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Gerrit-Change-Number: 60225 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 23 Dec 2021 15:34:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: remove board_id check for ALC5682I-VS
by Tim Wawrzynczak (Code Review) 23 Dec '21

23 Dec '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60128 ) Change subject: mb/google/brya/variants/primus: remove board_id check for ALC5682I-VS ...................................................................... mb/google/brya/variants/primus: remove board_id check for ALC5682I-VS The board ID check for audio codec is no longer required, therefore remove it. BUG=b:210705216 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60128 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/variant.c M src/mainboard/google/brya/variants/primus4es/variant.c 2 files changed, 4 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c index 4c2458a..90999ec 100644 --- a/src/mainboard/google/brya/variants/primus/variant.c +++ b/src/mainboard/google/brya/variants/primus/variant.c @@ -17,14 +17,11 @@ emmc_rtd3->enabled = 0; } -static void devtree_update_audio_codec(uint32_t board_ver) +static void devtree_update_audio_codec(void) { struct device *audio_codec = DEV_PTR(audio_codec); struct drivers_i2c_generic_config *config = audio_codec->chip_info; - if (board_ver <= 1) - return; - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) config->hid = "RTL5682"; } @@ -58,5 +55,5 @@ uint32_t board_ver = board_id(); disable_unused_gpios(); devtree_update_emmc_rtd3(board_ver); - devtree_update_audio_codec(board_ver); + devtree_update_audio_codec(); } diff --git a/src/mainboard/google/brya/variants/primus4es/variant.c b/src/mainboard/google/brya/variants/primus4es/variant.c index 4c2458a..90999ec 100644 --- a/src/mainboard/google/brya/variants/primus4es/variant.c +++ b/src/mainboard/google/brya/variants/primus4es/variant.c @@ -17,14 +17,11 @@ emmc_rtd3->enabled = 0; } -static void devtree_update_audio_codec(uint32_t board_ver) +static void devtree_update_audio_codec(void) { struct device *audio_codec = DEV_PTR(audio_codec); struct drivers_i2c_generic_config *config = audio_codec->chip_info; - if (board_ver <= 1) - return; - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) config->hid = "RTL5682"; } @@ -58,5 +55,5 @@ uint32_t board_ver = board_id(); disable_unused_gpios(); devtree_update_emmc_rtd3(board_ver); - devtree_update_audio_codec(board_ver); + devtree_update_audio_codec(); } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d Gerrit-Change-Number: 60128 Gerrit-PatchSet: 3 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59949 ) Change subject: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Copied from gimble set slow slew rate VCCIA and VCCGT to 8 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59949 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/gimble4es/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb index 5f8bd0e..5b022f6 100644 --- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -34,6 +34,13 @@ register "SaGv" = "SaGv_Enabled" register "PsysPmax" = "143" register "TcssAuxOri" = "1" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb Gerrit-Change-Number: 59949 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config
by Subrata Banik (Code Review) 23 Dec '21

23 Dec '21

Attention is currently required from: Nico Huber, Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 ) Change subject: soc/intel/jasperlake: Add CdClock frequency config ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/60009/comment/edd55f96_ce15e17a PS17, Line 212: params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff; > So is the comment in `src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h` wrong? […] I guess there are 2 problems 1. Default value what FSP assign to this UPD is 0xFF which is auto but help text says its '0'. 2. These entire UPD values are '0' based instead '1', meaning 0: 172.8 Mhz, 1: 180 Mhz, 2: 190 Mhz, ... etc. Is that correct understanding @Karthik? I remember reporting this problem to Intel FSP team earlier and its been fixed from TGL/ADL. I don't see the same issue in ADL https://github.com/coreboot/coreboot/blob/master/src/vendorcode/intel/fsp/f… -- To view, visit https://review.coreboot.org/c/coreboot/+/60009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Gerrit-Change-Number: 60009 Gerrit-PatchSet: 17 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 23 Dec 2021 15:05:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60135 ) Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync ...................................................................... soc/intel/alderlake: Add timestamp for cse_fw_sync The patch add timestamp around cse_fw_sync(). TEST=Verified on Brya, cbmem -t: 948:starting CSE firmware sync 1,381,577 (45,227) 949:finished CSE firmware sync 1,459,513 (77,936) Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index b9d08c8..ae83d49 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -16,6 +16,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <cpu/intel/cpu_ids.h> +#include <timestamp.h> #include <string.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ @@ -135,8 +136,11 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { + timestamp_add_now(TS_START_CSE_FW_SYNC); cse_fw_sync(); + timestamp_add_now(TS_END_CSE_FW_SYNC); + } /* * Set low maximum temp threshold value used for dynamic thermal sensor -- To view, visit https://review.coreboot.org/c/coreboot/+/60135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4 Gerrit-Change-Number: 60135 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/magolor: Add stylus function
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60185 ) Change subject: mb/google/dedede/var/magolor: Add stylus function ...................................................................... mb/google/dedede/var/magolor: Add stylus function Add the stylus field in fw_config. Update devicetree and gpio to handle stylus pen detection. BUG=b:167983049 TEST=Build firmware and check behavior as following: 1) Set the fw_config "bit4=1" for pen present: Wake up from suspend when pen is removed from the garage. Present the stylus menu when pen is removed from the garage. 2) Set the fw_config "bit4=0" for pen absent: Wake up and present menu will not work when pen is removed form the garage. Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185 Reviewed-by: Aseda Aboagye <aaboagye(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/magolor/Makefile.inc A src/mainboard/google/dedede/variants/magolor/gpio.c M src/mainboard/google/dedede/variants/magolor/overridetree.cb 4 files changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Aseda Aboagye: Looks good to me, but someone else must approve Ren Kuo: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index fa1ad8d..1b59ef0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -10,6 +10,10 @@ option DB_PORTS_1C 7 option DB_PORTS_1A_HDMI_LTE 8 end + field STYLUS 4 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end field TABLETMODE 10 option TABLETMODE_DISABLED 0 option TABLETMODE_ENABLED 1 diff --git a/src/mainboard/google/dedede/variants/magolor/Makefile.inc b/src/mainboard/google/dedede/variants/magolor/Makefile.inc index 24c75d1..3333383 100644 --- a/src/mainboard/google/dedede/variants/magolor/Makefile.inc +++ b/src/mainboard/google/dedede/variants/magolor/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/magolor/gpio.c b/src/mainboard/google/dedede/variants/magolor/gpio.c new file mode 100644 index 0000000..ae89085 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/gpio.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootstate.h> +#include <fw_config.h> +#include <commonlib/helpers.h> + +/* Pad configuration of stylus */ +static const struct pad_config stylus_det_pads[] = { + /* C12 : AP_PEN_DET_ODL (external pull-high) */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), +}; + +static void fw_config_handle(void *unused) +{ + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_PRESENT))) + gpio_configure_pads(stylus_det_pads, ARRAY_SIZE(stylus_det_pads)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index e5d75b1..66fc4ea 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -188,6 +188,19 @@ end end # I2C 0 device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe STYLUS STYLUS_PRESENT + end + end chip drivers/i2c/hid register "generic.hid" = ""ELAN6915"" register "generic.desc" = ""ELAN Touchscreen"" -- To view, visit https://review.coreboot.org/c/coreboot/+/60185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03 Gerrit-Change-Number: 60185 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/asrock/h77pro4-m: add new mainboard
by Michael Büchler (Code Review) 23 Dec '21

23 Dec '21

Michael Büchler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45317 ) Change subject: mb/asrock/h77pro4-m: add new mainboard ...................................................................... mb/asrock/h77pro4-m: add new mainboard This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. The port was initially done with autoport. It is quite similar to the ASRock B75 Pro4-M which is already supported by coreboot. Working: - Console output on the serial port of the Super I/O - Native RAM initialization with two DIMMs - Core i5-2500 CPU Not working: - Currently fails during PCIe bus scans Untested: - Ivy Bridge - All four DIMM slots - The rest Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> --- A src/mainboard/asrock/h77pro4-m/Kconfig A src/mainboard/asrock/h77pro4-m/Kconfig.name A src/mainboard/asrock/h77pro4-m/Makefile.inc A src/mainboard/asrock/h77pro4-m/acpi/ec.asl A src/mainboard/asrock/h77pro4-m/acpi/platform.asl A src/mainboard/asrock/h77pro4-m/acpi/superio.asl A src/mainboard/asrock/h77pro4-m/acpi_tables.c A src/mainboard/asrock/h77pro4-m/board_info.txt A src/mainboard/asrock/h77pro4-m/devicetree.cb A src/mainboard/asrock/h77pro4-m/dsdt.asl A src/mainboard/asrock/h77pro4-m/early_init.c A src/mainboard/asrock/h77pro4-m/gma-mainboard.ads A src/mainboard/asrock/h77pro4-m/gpio.c A src/mainboard/asrock/h77pro4-m/hda_verb.c A src/mainboard/asrock/h77pro4-m/mainboard.c 15 files changed, 612 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45317/1 diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig new file mode 100644 index 0000000..daa1526 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_H77PRO4_M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6776 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select DRIVERS_ASMEDIA_ASPM_BLACKLIST # FIXME copied from B75 Pro3M + +config MAINBOARD_DIR + string + default asrock/h77pro4-m + +config MAINBOARD_PART_NUMBER + string + default "H77 Pro4-M" + +config VGA_BIOS_FILE + string + default "pci8086,0152.rom" + +config VGA_BIOS_ID + string + default "8086,0152" + +#config DRAM_RESET_GATE_GPIO # FIXME: check this +# int +# default 60 +# +#config USBDEBUG_HCD_INDEX # FIXME: check this +# int +# default 2 +endif diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig.name b/src/mainboard/asrock/h77pro4-m/Kconfig.name new file mode 100644 index 0000000..03873b9 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H77PRO4_M + bool "H77 Pro4-M" diff --git a/src/mainboard/asrock/h77pro4-m/Makefile.inc b/src/mainboard/asrock/h77pro4-m/Makefile.inc new file mode 100644 index 0000000..a0d1155 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h77pro4-m/acpi/ec.asl b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asrock/h77pro4-m/acpi/platform.asl b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl new file mode 100644 index 0000000..146be65 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/h77pro4-m/acpi/superio.asl b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl new file mode 100644 index 0000000..1eae4b2 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e + +#define NCT6776_SHOW_SP1 1 +#define NCT6776_SHOW_KBC 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" diff --git a/src/mainboard/asrock/h77pro4-m/acpi_tables.c b/src/mainboard/asrock/h77pro4-m/acpi_tables.c new file mode 100644 index 0000000..f8364ab --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/h77pro4-m/board_info.txt b/src/mainboard/asrock/h77pro4-m/board_info.txt new file mode 100644 index 0000000..5f86088d --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb new file mode 100644 index 0000000..8c5d0e5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + #register "gfx.use_spread_spectrum_clock" = "0" # from B75 Pro3-M + #register "gfx" = "GMA_STATIC_DISPLAYS(0)" # from autoport + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1849 0x0100 + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0102 + end + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "0" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1849 0x1e31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x1e3a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x1e2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x8892 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1849 0x1e10 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE + subsystemid 0x1849 0x1e1a + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller + subsystemid 0x1849 0x1e1e + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x1e26 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1e4a + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # TODO verify + # global + irq 0x1c = 0x80 + irq 0x27 = 0xc0 + irq 0x2a = 0x62 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + # TODO verify + irq 0xe0 = 0x01 + irq 0xe3 = 0x14 + irq 0xe6 = 0x4c + #irq 0xe9 = 0x02 + irq 0xf0 = 0x20 + end + device pnp 2e.b off end # HWM, front panel LED + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on end # GPIO Push-Pull or Open-drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 on end # GPIOA + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1849 0x1e02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x1e22 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/asrock/h77pro4-m/dsdt.asl b/src/mainboard/asrock/h77pro4-m/dsdt.asl new file mode 100644 index 0000000..38f5325 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c new file mode 100644 index 0000000..ca79de8 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/common/nuvoton.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Set GPIOs on superio, enable UART */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x1b, 0x68); // bit 4 now cleared -> pin 95 GP24 + pnp_write_config(SERIAL_DEV, 0x1c, 0x80); // Pin 54 AFD#, pin 55 STB# + // default 0x64, vendor BIOS 0x5c + // bit 3 '1' -> CPUFANOUT push-pull instead of open drain + // bit 4 '1' -> SYSFANOUT push-pull instead of open drain + // bit 5 '0' -> AUXFANOUT open drain instead of push-pull + pnp_write_config(SERIAL_DEV, 0x24, 0x5c); // Pin 88-93 GP75-GP70, Pin 86-87 GP77-76 + pnp_write_config(SERIAL_DEV, 0x27, 0xc0); // Pin 88-93 GP75-GP70, Pin 86-87 GP77-76 + // default 0xc0 (bits 7,6 set), vendor BIOS 0x62 (bit 7 cleared, bit 1 set) + // bit 7 is '0' --> pins 29-36 COM A instead of GPIO8 (GP8*) + // bit 6 is '1' --> pins 116-123 are VIDI[7-0] + // bit 1 is '1' --> pin 56,57 are GP23,22 instead of MCLK,MDAT + // bit 0 is '0' --> pins 58,59 stay as KCLK,KDAT + pnp_write_config(SERIAL_DEV, 0x2a, 0x62); // Pin 29-36 COM A + pnp_write_config(SERIAL_DEV, 0x2b, 0x08); // Pin 81 GP32 instead of CPUPWRGD + pnp_write_config(SERIAL_DEV, 0x2c, 0x80); // Pin 113,115 GPA0,PECI instead of TSIC,TSID + + // FIXME 0x13,0x14 "Device IRQ Polarity Selection" are set by the vendor BIOS + + /* random note + * 24M_48M_SEL strap can be read on config reg 0x2f bit 0, it's '1' -> 48 MHz + * also LPT_EN is '1' on bit 1 of 0x2f -> LPT enabled + */ + + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + // generated by autoport + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1405); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h77pro4-m/gpio.c b/src/mainboard/asrock/h77pro4-m/gpio.c new file mode 100644 index 0000000..84f4564 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gpio.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c new file mode 100644 index 0000000..9998266 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19950), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h77pro4-m/mainboard.c b/src/mainboard/asrock/h77pro4-m/mainboard.c new file mode 100644 index 0000000..4322c1e --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/45317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Gerrit-Change-Number: 45317 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/Makefile.inc: Add warning for image built with no payload
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60025 ) Change subject: payloads/Makefile.inc: Add warning for image built with no payload ...................................................................... payloads/Makefile.inc: Add warning for image built with no payload Writing a coreboot image without a payload to a board's flash chip will result in a non-bootable system, so warn the user if this is the case. Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/Makefile.inc 1 file changed, 12 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index d89b5ba..83194c2 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -48,5 +48,16 @@ print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) +ifeq ($(CONFIG_PAYLOAD_NONE),y) +files_added:: warn_no_payload +endif + +warn_no_payload: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without a payload. Writing\n" + printf "a coreboot image without a payload to your board's\n" + printf "flash chip will result in a non-booting system. You\n" + printf "can use cbfstool to add a payload to the image.\n\n" + .PHONY: force-payload coreinfo nvramcui -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload -- To view, visit https://review.coreboot.org/c/coreboot/+/60025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057 Gerrit-Change-Number: 60025 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: AreYouLoco? <areyouloco(a)paranoici.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/guybrush/var/dewatt: update DRAM ID table
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60090 ) Change subject: mb/google/guybrush/var/dewatt: update DRAM ID table ...................................................................... mb/google/guybrush/var/dewatt: update DRAM ID table 1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL 2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants) BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc M src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt M src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt 3 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 26f27d5..313feb5 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -7,4 +7,4 @@ SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index 6a7b18b..dfd1aac 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -16,3 +16,5 @@ K4U6E3S4AB-MGCL 1 (0001) H54G46CYRBX267 1 (0001) MT53E512M32D1NP-046 WT:B 1 (0001) +H54G56CYRBX247 3 (0011) +K4UBE3D4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt index 361e3f5..298e58b 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt @@ -11,3 +11,4 @@ H54G46CYRBX267 MT53E512M32D1NP-046 WT:B H54G56CYRBX247 +K4UBE3D4AB-MGCL 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Gerrit-Change-Number: 60090 Gerrit-PatchSet: 7 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update telemetry settings
by Felix Held (Code Review) 23 Dec '21

23 Dec '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60243 ) Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings ...................................................................... mb/google/guybrush/var/nipperkin: update telemetry settings Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 19c6fe1..c7917ae 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -61,10 +61,10 @@ register "sustained_power_limit_mW" = "15000" register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcrvddfull_scale_current_mA" = "73457" #mA - register "telemetry_vddcrvddoffset" = "291" - register "telemetry_vddcrsocfull_scale_current_mA" = "30761" #mA - register "telemetry_vddcrsocoffset" = "834" + register "telemetry_vddcrvddfull_scale_current_mA" = "73331" #mA + register "telemetry_vddcrvddoffset" = "1893" + register "telemetry_vddcrsocfull_scale_current_mA" = "31955" #mA + register "telemetry_vddcrsocoffset" = "852" # I2C Config #+-------------------+---------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/60243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Gerrit-Change-Number: 60243 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth - Personal <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2021