coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/volteer: allow MKBP devices and disable TBMC device
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58741 ) Change subject: mb/google/volteer: allow MKBP devices and disable TBMC device ...................................................................... mb/google/volteer: allow MKBP devices and disable TBMC device Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:171365305 TEST=manual test on Volteer: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Boris Mittelberg <bmbm(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Boris Mittelberg: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index 5ae32fa..6eca8bc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -56,13 +56,13 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -/* Enable Tablet switch */ -#define EC_ENABLE_TBMC_DEVICE - #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e Gerrit-Change-Number: 58741 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Configure EC in RW GPIO
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58099 ) Change subject: mb/intel/adlrvp: Configure EC in RW GPIO ...................................................................... mb/intel/adlrvp: Configure EC in RW GPIO EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/early_gpio.c M src/mainboard/intel/adlrvp/early_gpio_m.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/include/baseboard/gpio.h 5 files changed, 13 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index d963c73..244b942 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -12,9 +12,12 @@ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {-1, ACTIVE_HIGH, 0, "EC in RW"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)) + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + else + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1); } #if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c index 7576ff1..68d69af 100644 --- a/src/mainboard/intel/adlrvp/early_gpio.c +++ b/src/mainboard/intel/adlrvp/early_gpio.c @@ -16,6 +16,9 @@ /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* CPU PCIe VGPIO for RP0 */ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index 915240c..3798593 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -17,6 +17,9 @@ /* H13 : CPU_SSD_RST# */ PAD_CFG_GPO(GPP_H13, 0, PLTRST), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* CPU PCIe VGPIO for RP0 */ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 1996683..c4d946b 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -38,8 +38,6 @@ PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* THC1_SPI2_INTB */ PAD_CFG_GPI(GPP_E17, NONE, PLTRST), - /* EC_SMI_N */ - PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), /* EC_SLP_S0_CS_N */ PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* WIFI RF KILL */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index de0adf6..9a1c585 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,4 +12,6 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +#define GPIO_EC_IN_RW GPP_E7 + #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Gerrit-Change-Number: 58099 Gerrit-PatchSet: 14 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Update STT coefficients
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58674 ) Change subject: mb/google/guybrush: Update STT coefficients ...................................................................... mb/google/guybrush: Update STT coefficients Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 8a9543d..7fb3c7e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -52,23 +52,23 @@ register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" register "stt_min_limit" = "0" - register "stt_m1" = "0x0319" - register "stt_m2" = "0x01A0" + register "stt_m1" = "0x03A0" + register "stt_m2" = "0xFFC9" register "stt_m3" = "0" register "stt_m4" = "0" register "stt_m5" = "0" register "stt_m6" = "0" - register "stt_c_apu" = "0xE99F" + register "stt_c_apu" = "0x0901" register "stt_c_gpu" = "0" register "stt_c_hs2" = "0" - register "stt_alpha_apu" = "0xCCD" + register "stt_alpha_apu" = "0x199A" register "stt_alpha_gpu" = "0" register "stt_alpha_hs2" = "0" register "stt_skin_temp_apu" = "0x2D00" register "stt_skin_temp_gpu" = "0" register "stt_skin_temp_hs2" = "0" - register "stt_error_coeff" = "0xD" - register "stt_error_rate_coefficient" = "0x8F6" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0xCCD" register "system_configuration" = "2" 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Gerrit-Change-Number: 58674 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/system76/*: CMOS: Drop power_on_after_fail option
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58673 ) Change subject: mb/system76/*: CMOS: Drop power_on_after_fail option ...................................................................... mb/system76/*: CMOS: Drop power_on_after_fail option Our boards do not boot if power_on_after_fail=Disable. Drop the option and use the default of powering on. Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/addw1/cmos.default M src/mainboard/system76/addw1/cmos.layout M src/mainboard/system76/cml-u/cmos.default M src/mainboard/system76/cml-u/cmos.layout M src/mainboard/system76/darp7/cmos.default M src/mainboard/system76/darp7/cmos.layout M src/mainboard/system76/galp5/cmos.default M src/mainboard/system76/galp5/cmos.layout M src/mainboard/system76/gaze15/cmos.default M src/mainboard/system76/gaze15/cmos.layout M src/mainboard/system76/lemp10/cmos.default M src/mainboard/system76/lemp10/cmos.layout M src/mainboard/system76/lemp9/cmos.default M src/mainboard/system76/lemp9/cmos.layout M src/mainboard/system76/oryp5/cmos.default M src/mainboard/system76/oryp5/cmos.layout M src/mainboard/system76/oryp6/cmos.default M src/mainboard/system76/oryp6/cmos.layout M src/mainboard/system76/whl-u/cmos.default M src/mainboard/system76/whl-u/cmos.layout 20 files changed, 0 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/cmos.default b/src/mainboard/system76/addw1/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/addw1/cmos.default +++ b/src/mainboard/system76/addw1/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/addw1/cmos.layout b/src/mainboard/system76/addw1/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/addw1/cmos.layout +++ b/src/mainboard/system76/addw1/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/cml-u/cmos.default b/src/mainboard/system76/cml-u/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/cml-u/cmos.default +++ b/src/mainboard/system76/cml-u/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/cml-u/cmos.layout b/src/mainboard/system76/cml-u/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/cml-u/cmos.layout +++ b/src/mainboard/system76/cml-u/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/darp7/cmos.default b/src/mainboard/system76/darp7/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/darp7/cmos.default +++ b/src/mainboard/system76/darp7/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/darp7/cmos.layout b/src/mainboard/system76/darp7/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/darp7/cmos.layout +++ b/src/mainboard/system76/darp7/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/galp5/cmos.default b/src/mainboard/system76/galp5/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/galp5/cmos.default +++ b/src/mainboard/system76/galp5/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/galp5/cmos.layout b/src/mainboard/system76/galp5/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/galp5/cmos.layout +++ b/src/mainboard/system76/galp5/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/gaze15/cmos.default b/src/mainboard/system76/gaze15/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/gaze15/cmos.default +++ b/src/mainboard/system76/gaze15/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/gaze15/cmos.layout b/src/mainboard/system76/gaze15/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/gaze15/cmos.layout +++ b/src/mainboard/system76/gaze15/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/lemp10/cmos.default b/src/mainboard/system76/lemp10/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/lemp10/cmos.default +++ b/src/mainboard/system76/lemp10/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/lemp10/cmos.layout b/src/mainboard/system76/lemp10/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/lemp10/cmos.layout +++ b/src/mainboard/system76/lemp10/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/lemp9/cmos.default b/src/mainboard/system76/lemp9/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/lemp9/cmos.default +++ b/src/mainboard/system76/lemp9/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/lemp9/cmos.layout +++ b/src/mainboard/system76/lemp9/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/oryp5/cmos.default b/src/mainboard/system76/oryp5/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/oryp5/cmos.default +++ b/src/mainboard/system76/oryp5/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/oryp5/cmos.layout b/src/mainboard/system76/oryp5/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/oryp5/cmos.layout +++ b/src/mainboard/system76/oryp5/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/oryp6/cmos.default b/src/mainboard/system76/oryp6/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/oryp6/cmos.default +++ b/src/mainboard/system76/oryp6/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/oryp6/cmos.layout b/src/mainboard/system76/oryp6/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/oryp6/cmos.layout +++ b/src/mainboard/system76/oryp6/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 diff --git a/src/mainboard/system76/whl-u/cmos.default b/src/mainboard/system76/whl-u/cmos.default index d564953..06b0433 100644 --- a/src/mainboard/system76/whl-u/cmos.default +++ b/src/mainboard/system76/whl-u/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback debug_level=Debug -power_on_after_fail=Enable diff --git a/src/mainboard/system76/whl-u/cmos.layout b/src/mainboard/system76/whl-u/cmos.layout index ca7c7a4..ac81752 100644 --- a/src/mainboard/system76/whl-u/cmos.layout +++ b/src/mainboard/system76/whl-u/cmos.layout @@ -11,7 +11,6 @@ # RTC_CLK_ALTCENTURY 400 8 r 0 century -409 2 e 7 power_on_after_fail 412 4 e 6 debug_level 984 16 h 0 check_sum @@ -30,10 +29,6 @@ 6 7 Debug 6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep - checksums checksum 408 983 984 -- To view, visit https://review.coreboot.org/c/coreboot/+/58673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Gerrit-Change-Number: 58673 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/block/cpu: Add support for cbfs_cache region
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56578 ) Change subject: soc/amd/common/block/cpu: Add support for cbfs_cache region ...................................................................... soc/amd/common/block/cpu: Add support for cbfs_cache region This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 11b6c8c..3dd1e33 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -24,6 +24,11 @@ string default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" +config CBFS_CACHE_SIZE + hex + help + The size of the cbfs_cache region. + config PAYLOAD_PRELOAD_CACHE_SIZE hex default 0x30000 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 005bde0..a542b7d 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -25,6 +25,10 @@ * | | * reserved_dram_end +--------------------------------+ * | | + * | cbfs_cache (if reqd) | + * | (CBFS_CACHE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE + * | | * | verstage (if reqd) | * | (VERSTAGE_SIZE) | * +--------------------------------+ VERSTAGE_ADDR @@ -95,6 +99,11 @@ VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif +#if CONFIG_CBFS_CACHE_SIZE > 0 + . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); + CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE) +#endif + EARLY_RESERVED_DRAM_END(.) #if CONFIG(PAYLOAD_PRELOAD) -- To view, visit https://review.coreboot.org/c/coreboot/+/56578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Gerrit-Change-Number: 56578 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: psp_verstage: convert relative address in EFS2
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58316 ) Change subject: psp_verstage: convert relative address in EFS2 ...................................................................... psp_verstage: convert relative address in EFS2 Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/common/block/include/amdblocks/psp_efs.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/include/soc/iomap.h 4 files changed, 13 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index a4f0f30..f83f13a 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -36,10 +36,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800 -#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 1a6059a..a3996cb 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -29,6 +29,8 @@ uint32_t reserved:31; } __attribute__((packed)); +#define EFS_SECOND_GEN 0 + /* Copied from coreboot/util/amdfwtool.h */ struct embedded_firmware { uint32_t signature; /* 0x55aa55aa */ diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index c03cf9b..9f27159 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -10,6 +10,7 @@ #include <console/console.h> #include <fmap.h> #include <pc80/mc146818rtc.h> +#include <soc/iomap.h> #include <soc/psp_transfer.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> @@ -121,6 +122,12 @@ return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; } + /* EFS2 uses relative address and PSP isn't happy with that */ + if (ef_table->efs_gen.gen == EFS_SECOND_GEN) { + psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK); + bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK); + } + if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) { printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n"); return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1577568..93f2874 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -61,10 +61,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800 -#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95813beba7278480e6640599fcf7445923259361 Gerrit-Change-Number: 58316 Gerrit-PatchSet: 7 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: google/trogdor: Add backlight support for Parade ps8640
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58624 ) Change subject: google/trogdor: Add backlight support for Parade ps8640 ...................................................................... google/trogdor: Add backlight support for Parade ps8640 Add backlight support in ps8640 through the AUX channel using eDP DPCD registers. BUG=b:202966352 BRANCH=trogdor TEST=verified firmware screen works on homestar rev4 Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2 Signed-off-by: xuxinxiong <xuxinxiong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/parade/ps8640/ps8640.c M src/drivers/parade/ps8640/ps8640.h M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c A src/include/dp_aux.h M src/lib/Makefile.inc A src/lib/dp_aux.c 6 files changed, 219 insertions(+), 77 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index 93121f2..587eae1 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -5,7 +5,7 @@ #include <edid.h> #include <console/console.h> #include <timer.h> - +#include <dp_aux.h> #include "ps8640.h" int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out) @@ -80,3 +80,101 @@ return 0; } + +static cb_err_t ps8640_bridge_aux_request(uint8_t bus, + uint8_t chip, + unsigned int target_reg, + unsigned int total_size, + enum aux_request request, + uint8_t *data) +{ + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + int ret; + + if (target_reg & ~SWAUX_ADDR_MASK) + return CB_ERR; + + while (total_size) { + length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES); + total_size -= length; + + ret = i2c_writeb(bus, chip, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); + if (ret) + return CB_ERR; + + enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size); + if (i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_23_16, + (target_reg >> 16) | (cmd << 4)) || + i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_15_8, target_reg >> 8) || + i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_7_0, target_reg)) { + return CB_ERR; + } + + if (dp_aux_request_is_write(request)) { + reg = PAGE0_SWAUX_WDATA; + for (i = 0; i < length; i++) { + ret = i2c_writeb(bus, chip, reg++, *data++); + if (ret) + return CB_ERR; + } + } else { + if (length == 0) + i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, SWAUX_NO_PAYLOAD); + else + i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, length - 1); + } + + ret = i2c_writeb(bus, chip, PAGE0_SWAUX_CTRL, SWAUX_SEND); + if (ret) + return CB_ERR; + + if (!wait_ms(100, !i2c_readb(bus, chip, PAGE0_SWAUX_CTRL, &buf) && + !(buf & SWAUX_SEND))) + return CB_ERR; + + if (i2c_readb(bus, chip, PAGE0_SWAUX_STATUS, &buf)) + return CB_ERR; + + switch (buf & SWAUX_STATUS_MASK) { + case SWAUX_STATUS_NACK: + case SWAUX_STATUS_I2C_NACK: + case SWAUX_STATUS_INVALID: + case SWAUX_STATUS_TIMEOUT: + return CB_ERR; + case SWAUX_STATUS_ACKM: + length = buf & SWAUX_M_MASK; + break; + } + + if (length && !dp_aux_request_is_write(request)) { + reg = PAGE0_SWAUX_RDATA; + for (i = 0; i < length; i++) { + if (i2c_readb(bus, chip, reg++, &buf)) + return CB_ERR; + *data++ = buf; + } + } + } + + return CB_SUCCESS; +} + +void ps8640_backlight_enable(uint8_t bus, uint8_t chip) +{ + uint8_t val; + + val = DP_BACKLIGHT_CONTROL_MODE_DPCD; + ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1, + DPCD_WRITE, &val); + + val = 0xff; + ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1, + DPCD_WRITE, &val); + + val = DP_BACKLIGHT_ENABLE; + ps8640_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1, + DPCD_WRITE, &val); +} diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index 06daad4..fb78be6 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -24,11 +24,33 @@ }; enum { - EDID_LENGTH = 128, - EDID_I2C_ADDR = 0x50, - EDID_EXTENSION_FLAG = 0x7e, + PAGE0_AUXCH_CFG3 = 0x76, + AUXCH_CFG3_RESET = 0xff, + PAGE0_SWAUX_ADDR_7_0 = 0x7d, + PAGE0_SWAUX_ADDR_15_8 = 0x7e, + PAGE0_SWAUX_ADDR_23_16 = 0x7f, + SWAUX_ADDR_MASK = 0xfffff, + PAGE0_SWAUX_LENGTH = 0x80, + SWAUX_LENGTH_MASK = 0xf, + SWAUX_NO_PAYLOAD = BIT(7), + PAGE0_SWAUX_WDATA = 0x81, + PAGE0_SWAUX_RDATA = 0x82, + PAGE0_SWAUX_CTRL = 0x83, + SWAUX_SEND = BIT(0), + PAGE0_SWAUX_STATUS = 0x84, + SWAUX_M_MASK = 0x1f, + SWAUX_STATUS_MASK = (0x7 << 5), + SWAUX_STATUS_NACK = (0x1 << 5), + SWAUX_STATUS_DEFER = (0x2 << 5), + SWAUX_STATUS_ACKM = (0x3 << 5), + SWAUX_STATUS_INVALID = (0x4 << 5), + SWAUX_STATUS_I2C_NACK = (0x5 << 5), + SWAUX_STATUS_I2C_DEFER = (0x6 << 5), + SWAUX_STATUS_TIMEOUT = (0x7 << 5), }; int ps8640_init(uint8_t bus, uint8_t chip); int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out); +void ps8640_backlight_enable(uint8_t bus, uint8_t chip); + #endif diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 2ba0977..c4c4088 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -4,6 +4,7 @@ #include <delay.h> #include <endian.h> #include <device/i2c_simple.h> +#include <dp_aux.h> #include <edid.h> #include <timer.h> #include <types.h> @@ -31,14 +32,6 @@ #define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ #define DP_LANE_COUNT_MASK 0xf -/* Backlight configuration */ -#define DP_BACKLIGHT_MODE_SET 0x721 -#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3 -#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2 -#define DP_DISPLAY_CONTROL_REGISTER 0x720 -#define DP_BACKLIGHT_ENABLE 0x1 -#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722 - /* link configuration */ #define DP_LINK_BW_SET 0x100 #define DP_LINK_BW_1_62 0x06 @@ -132,17 +125,6 @@ VSTREAM_ENABLE = 1, }; -enum i2c_over_aux { - I2C_OVER_AUX_WRITE_MOT_0 = 0x0, - I2C_OVER_AUX_READ_MOT_0 = 0x1, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2, - I2C_OVER_AUX_WRITE_MOT_1 = 0x4, - I2C_OVER_AUX_READ_MOT_1 = 0x5, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6, - NATIVE_AUX_WRITE = 0x8, - NATIVE_AUX_READ = 0x9, -}; - enum aux_cmd_status { NAT_I2C_FAIL = 1 << 6, AUX_SHORT = 1 << 5, @@ -166,21 +148,6 @@ REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, }; -enum aux_request { - DPCD_READ, - DPCD_WRITE, - I2C_RAW_READ, - I2C_RAW_WRITE, - I2C_RAW_READ_AND_STOP, - I2C_RAW_WRITE_AND_STOP, -}; - -enum { - EDID_LENGTH = 128, - EDID_I2C_ADDR = 0x50, - EDID_EXTENSION_FLAG = 0x7e, -}; - /* * LUT index corresponds to register value and LUT values corresponds * to dp data rate supported by the bridge in Mbps unit. @@ -189,41 +156,6 @@ 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -static bool request_is_write(enum aux_request request) -{ - switch (request) { - case I2C_RAW_WRITE_AND_STOP: - case I2C_RAW_WRITE: - case DPCD_WRITE: - return true; - default: - return false; - } -} - -static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this) -{ - switch (request) { - case I2C_RAW_WRITE_AND_STOP: - if (!remaining_after_this) - return I2C_OVER_AUX_WRITE_MOT_0; - /* fallthrough */ - case I2C_RAW_WRITE: - return I2C_OVER_AUX_WRITE_MOT_1; - case I2C_RAW_READ_AND_STOP: - if (!remaining_after_this) - return I2C_OVER_AUX_READ_MOT_0; - /* fallthrough */ - case I2C_RAW_READ: - return I2C_OVER_AUX_READ_MOT_1; - case DPCD_WRITE: - return NATIVE_AUX_WRITE; - case DPCD_READ: - default: - return NATIVE_AUX_READ; - } -} - static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, uint8_t chip, unsigned int target_reg, @@ -241,10 +173,10 @@ NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT); while (total_size) { - length = MIN(total_size, 16); + length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES); total_size -= length; - enum i2c_over_aux cmd = get_aux_cmd(request, total_size); + enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size); if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) || i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) || i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) || @@ -252,7 +184,7 @@ i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length)) return CB_ERR; - if (request_is_write(request)) { + if (dp_aux_request_is_write(request)) { reg = SN_AUX_WDATA_REG_0; for (i = 0; i < length; i++) if (i2c_writeb(bus, chip, reg++, *data++)) @@ -273,7 +205,7 @@ return CB_ERR; } - if (!request_is_write(request)) { + if (!dp_aux_request_is_write(request)) { reg = SN_AUX_RDATA_REG_0; for (i = 0; i < length; i++) { if (i2c_readb(bus, chip, reg++, &buf)) diff --git a/src/include/dp_aux.h b/src/include/dp_aux.h new file mode 100644 index 0000000..ce93383 --- /dev/null +++ b/src/include/dp_aux.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DP_AUX_H_ +#define _DP_AUX_H_ + +#include <types.h> + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +enum i2c_over_aux { + I2C_OVER_AUX_WRITE_MOT_0 = 0x0, + I2C_OVER_AUX_READ_MOT_0 = 0x1, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2, + I2C_OVER_AUX_WRITE_MOT_1 = 0x4, + I2C_OVER_AUX_READ_MOT_1 = 0x5, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6, + NATIVE_AUX_WRITE = 0x8, + NATIVE_AUX_READ = 0x9, +}; + +enum aux_request { + DPCD_READ, + DPCD_WRITE, + I2C_RAW_READ, + I2C_RAW_WRITE, + I2C_RAW_READ_AND_STOP, + I2C_RAW_WRITE_AND_STOP, +}; + +/* Backlight configuration */ +#define DP_BACKLIGHT_MODE_SET 0x721 +#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3 +#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2 +#define DP_DISPLAY_CONTROL_REGISTER 0x720 +#define DP_BACKLIGHT_ENABLE 0x1 +#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722 + +#define DP_AUX_MAX_PAYLOAD_BYTES 16 + + +bool dp_aux_request_is_write(enum aux_request request); +enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 693a526..0f96aeb 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -147,6 +147,7 @@ ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c +ramstage-y += dp_aux.c ramstage-y += edid.c ramstage-y += edid_fill_fb.c ramstage-y += memrange.c diff --git a/src/lib/dp_aux.c b/src/lib/dp_aux.c new file mode 100644 index 0000000..ee3ac8ab --- /dev/null +++ b/src/lib/dp_aux.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <dp_aux.h> +#include <console/console.h> +#include <timer.h> + +bool dp_aux_request_is_write(enum aux_request request) +{ + switch (request) { + case I2C_RAW_WRITE_AND_STOP: + case I2C_RAW_WRITE: + case DPCD_WRITE: + return true; + default: + return false; + } +} + +enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this) +{ + switch (request) { + case I2C_RAW_WRITE_AND_STOP: + if (!remaining_after_this) + return I2C_OVER_AUX_WRITE_MOT_0; + /* fallthrough */ + case I2C_RAW_WRITE: + return I2C_OVER_AUX_WRITE_MOT_1; + case I2C_RAW_READ_AND_STOP: + if (!remaining_after_this) + return I2C_OVER_AUX_READ_MOT_0; + /* fallthrough */ + case I2C_RAW_READ: + return I2C_OVER_AUX_READ_MOT_1; + case DPCD_WRITE: + return NATIVE_AUX_WRITE; + case DPCD_READ: + default: + return NATIVE_AUX_READ; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2 Gerrit-Change-Number: 58624 Gerrit-PatchSet: 9 Gerrit-Owner: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Correct AT24 NVM address size
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58769 ) Change subject: mb/google/brya: Correct AT24 NVM address size ...................................................................... mb/google/brya: Correct AT24 NVM address size Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0E to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index f3b7925..0052d90 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -320,7 +320,7 @@ register "nvm_size" = "0x2800" register "nvm_pagesize" = "0x01" register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" + register "nvm_width" = "0x10" device i2c 58 on end end 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Gerrit-Change-Number: 58769 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/hda: Remove the weak function
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58772 ) Change subject: amd/hda: Remove the weak function ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/stoneyridge/northbridge.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131990): https://review.coreboot.org/c/coreboot/+/58772/comment/a41045b0_e838c11c PS3, Line 470: /* Look for the hda pci configration define. */ 'configration' may be misspelled - perhaps 'configuration'? -- To view, visit https://review.coreboot.org/c/coreboot/+/58772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Gerrit-Change-Number: 58772 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 08:16:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask: add the mkbp device
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58744 ) Change subject: mb/google/brask: add the mkbp device ...................................................................... mb/google/brask: add the mkbp device In order to let the ec passing the key event like recovery and power key to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP device. BUG=b:204519353, b:204512547 BRANCH=None TEST=pressed recovery key and power button in the OS and checked the UI behavior. Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h index 43bf951..2ea04ee 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h @@ -32,6 +32,8 @@ /* * ACPI related definitions for ASL code. */ +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/58744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0 Gerrit-Change-Number: 58744 Gerrit-PatchSet: 3 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2021