coreboot-gerrit November 2021

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Change in coreboot[master]: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58568 ) Change subject: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree ...................................................................... mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 49fd515..f6ac8b7 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -51,8 +51,6 @@ register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "0x00" @@ -74,16 +72,14 @@ register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[2]" = "true" register "PcieRpLtrDisable[3]" = "true" - register "PcieRpLtrDisable[4]" = "true" - register "PcieRpLtrDisable[5]" = "true" + register "PcieRpLtrDisable[6]" = "true" # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" @@ -157,8 +153,6 @@ device pci 1c.1 on end # RP2 (pcie0 single VC) device pci 1c.2 on end # RP3 (pcie0 single VC) device pci 1c.3 on end # RP4 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) - device pci 1c.5 on end # RP6 (pcie2 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1e.0 on end # UART0 -- To view, visit https://review.coreboot.org/c/coreboot/+/58568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Gerrit-Change-Number: 58568 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl1: Clean up devicetree
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58567 ) Change subject: mb/siemens/mc_ehl1: Clean up devicetree ...................................................................... mb/siemens/mc_ehl1: Clean up devicetree There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 4 insertions(+), 74 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index be98a15..49fd515 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -120,8 +120,8 @@ }" register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" @@ -138,74 +138,20 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 08.0 off end # GNA - device pci 09.0 off end # CPU Intel Trace Hub - - device pci 10.0 off end # I2C6 - device pci 10.1 off end # I2C7 - device pci 10.5 on end # Integrated Error Handler - - device pci 11.0 off end # Intel PSE UART0 - device pci 11.1 off end # Intel PSE UART1 - device pci 11.2 off end # Intel PSE UART2 - device pci 11.3 off end # Intel PSE UART3 - device pci 11.4 off end # Intel PSE UART4 - device pci 11.5 off end # Intel PSE UART5 - device pci 11.6 off end # Intel PSE IS20 - device pci 11.7 off end # Intel PSE IS21 - - device pci 12.0 off end # GSPI2 - device pci 12.3 on end # Management Engine UMA Access - device pci 12.4 on end # Management Engine PTT DMA Controller - device pci 12.5 off end # UFS0 - device pci 12.7 off end # UFS1 - - device pci 13.0 off end # Intel PSE GSPI0 - device pci 13.1 off end # Intel PSE GSPI1 - device pci 13.2 off end # Intel PSE GSPI2 - device pci 13.3 off end # Intel PSE GSPI3 - device pci 13.4 off end # Intel PSE GPIO0 - device pci 13.5 off end # Intel PSE GPIO1 device pci 14.0 on end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI (OTG) device pci 15.0 off end # I2C0 device pci 15.1 on end # I2C1 - device pci 15.2 off end # I2C2 - device pci 15.3 off end # I2C3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 on end # Management Engine Interface 4 + device pci 16.0 hidden end # Management Engine Interface 1 device pci 17.0 on end # SATA - device pci 18.0 off end # Intel PSE I2C7 - device pci 18.1 off end # Intel PSE CAN0 - device pci 18.2 off end # Intel PSE CAN1 - device pci 18.3 off end # Intel PSE QEP0 - device pci 18.4 off end # Intel PSE QEP1 - device pci 18.5 off end # Intel PSE QEP2 - device pci 18.6 off end # Intel PSE QEP3 - device pci 19.0 on end # I2C4 - device pci 19.1 off end # I2C5 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC - device pci 1a.1 off end # SD - device pci 1a.3 off end # Intel Safety Island - - device pci 1b.0 off end # Intel PSE I2C0 - device pci 1b.1 off end # Intel PSE I2C1 - device pci 1b.2 off end # Intel PSE I2C2 - device pci 1b.3 off end # Intel PSE I2C3 - device pci 1b.4 off end # Intel PSE I2C4 - device pci 1b.5 off end # Intel PSE I2C5 - device pci 1b.6 off end # Intel PSE I2C6 device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) @@ -215,31 +161,16 @@ device pci 1c.5 on end # RP6 (pcie2 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) - device pci 1d.0 off end # Intel PSE IPC (local host to PSE) - device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 - device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 - device pci 1d.3 off end # Intel PSE DMA0 - device pci 1d.4 off end # Intel PSE DMA1 - device pci 1d.5 off end # Intel PSE DMA2 - device pci 1d.6 off end # Intel PSE PWM - device pci 1d.7 off end # Intel PSE ADC - device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.2 off end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1e.4 on end # PCH Time-Sensitive Networking GbE - device pci 1e.6 on end # HPET - device pci 1e.7 on end # IOAPIC + device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 off end # Intel cAVS/HDA device pci 1f.4 on # SMBus # Enable external RTC chip chip drivers/i2c/rx6110sa @@ -257,6 +188,5 @@ end end device pci 1f.5 on end # PCH SPI (flash & TPM) - device pci 1f.7 off end # PCH Intel Trace Hub end end -- To view, visit https://review.coreboot.org/c/coreboot/+/58567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247 Gerrit-Change-Number: 58567 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58601 ) Change subject: lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() ...................................................................... lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width() Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/include/dimm_info_util.h M src/include/spd.h M src/lib/dimm_info_util.c M src/soc/amd/common/fsp/dmi.c M src/soc/amd/common/pi/amd_late_init.c M src/soc/intel/common/smbios.c M tests/lib/dimm_info_util-test.c 7 files changed, 52 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/include/dimm_info_util.h b/src/include/dimm_info_util.h index d20e8cd..04e9336 100644 --- a/src/include/dimm_info_util.h +++ b/src/include/dimm_info_util.h @@ -12,7 +12,7 @@ * Use this when setting dimm_info.bus_width if the raw SPD values are not * available. */ -uint8_t smbios_bus_width_to_spd_width(uint16_t total_width, +uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width, uint16_t data_width); /** diff --git a/src/include/spd.h b/src/include/spd.h index ec5296e..af3072e 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -209,5 +209,6 @@ #define SPD_MINI_UDIMM 0x20 #define SPD_ECC_8BIT (1<<3) +#define SPD_ECC_8BIT_LP5_DDR5 (1<<4) #endif diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c index fb8e06f..0e7cc12 100644 --- a/src/lib/dimm_info_util.c +++ b/src/lib/dimm_info_util.c @@ -5,7 +5,8 @@ #include <spd.h> #include <console/console.h> -uint8_t smbios_bus_width_to_spd_width(uint16_t total_width, uint16_t data_width) +uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width, + uint16_t data_width) { uint8_t out; @@ -38,7 +39,10 @@ switch (extension_bits) { case 8: - out |= SPD_ECC_8BIT; + if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5) + out |= SPD_ECC_8BIT_LP5_DDR5; + else + out |= SPD_ECC_8BIT; break; case 0: /* No extension bits */ diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index 61d43f7..223cce1 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -54,8 +54,8 @@ dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); - dimm->bus_width = - smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, + dmi17->DataWidth); dimm->mod_id = dmi17->ManufacturerIdCode; diff --git a/src/soc/amd/common/pi/amd_late_init.c b/src/soc/amd/common/pi/amd_late_init.c index 25aaea3..3714404 100644 --- a/src/soc/amd/common/pi/amd_late_init.c +++ b/src/soc/amd/common/pi/amd_late_init.c @@ -38,8 +38,8 @@ dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); - dimm->bus_width = - smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, + dmi17->DataWidth); dimm->mod_id = dmi17->ManufacturerIdCode; diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index a2b4a0b..213be65 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -65,5 +65,5 @@ if (ecc_support) total_width += EXTENSION_BUS_WIDTH_8BITS; - dimm->bus_width = smbios_bus_width_to_spd_width(total_width, data_width); + dimm->bus_width = smbios_bus_width_to_spd_width(ddr_type, total_width, data_width); } diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 4b3f979..25800d9 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -4,28 +4,51 @@ #include <spd.h> #include <tests/test.h> -static void test_smbios_bus_width_to_spd_width(void **state) +static void test_smbios_bus_width_to_spd_width_parametrized(smbios_memory_type ddr_type) { /* Non-ECC variants */ - assert_int_equal(MEMORY_BUS_WIDTH_64, smbios_bus_width_to_spd_width(64, 64)); - assert_int_equal(MEMORY_BUS_WIDTH_32, smbios_bus_width_to_spd_width(32, 32)); - assert_int_equal(MEMORY_BUS_WIDTH_16, smbios_bus_width_to_spd_width(16, 16)); - assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(8, 8)); + assert_int_equal(MEMORY_BUS_WIDTH_64, smbios_bus_width_to_spd_width(ddr_type, 64, 64)); + assert_int_equal(MEMORY_BUS_WIDTH_32, smbios_bus_width_to_spd_width(ddr_type, 32, 32)); + assert_int_equal(MEMORY_BUS_WIDTH_16, smbios_bus_width_to_spd_width(ddr_type, 16, 16)); + assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(ddr_type, 8, 8)); /* Incorrect data width. Fallback to 8-bit */ - assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(15, 15)); + assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(ddr_type, 15, 15)); /* ECC variants */ - assert_int_equal(MEMORY_BUS_WIDTH_64 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(64 + 8, 64)); - assert_int_equal(MEMORY_BUS_WIDTH_32 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(32 + 8, 32)); - assert_int_equal(MEMORY_BUS_WIDTH_16 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(16 + 8, 16)); - assert_int_equal(MEMORY_BUS_WIDTH_8 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(8 + 8, 8)); + uint8_t extension_8bits = SPD_ECC_8BIT; + if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5) + extension_8bits = SPD_ECC_8BIT_LP5_DDR5; + + assert_int_equal(MEMORY_BUS_WIDTH_64 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 64 + 8, 64)); + assert_int_equal(MEMORY_BUS_WIDTH_32 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 32 + 8, 32)); + assert_int_equal(MEMORY_BUS_WIDTH_16 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 16 + 8, 16)); + assert_int_equal(MEMORY_BUS_WIDTH_8 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 8 + 8, 8)); /* Incorrect data width. Fallback to 8-bit */ - assert_int_equal(MEMORY_BUS_WIDTH_8 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(15 + 8, 15)); + assert_int_equal(MEMORY_BUS_WIDTH_8 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 15 + 8, 15)); +} + +static void test_smbios_bus_width_to_spd_width(void **state) +{ + smbios_memory_type memory_type[] = { + MEMORY_TYPE_DDR2, + MEMORY_TYPE_DDR3, + MEMORY_TYPE_DDR4, + MEMORY_TYPE_DDR5, + MEMORY_TYPE_LPDDR3, + MEMORY_TYPE_LPDDR4, + MEMORY_TYPE_LPDDR5, + }; + + for (int i = 0; i < ARRAY_SIZE(memory_type); i++) { + print_message("test_smbios_bus_width_to_spd_width_parametrized(%d)\n", + memory_type[i]); + test_smbios_bus_width_to_spd_width_parametrized(memory_type[i]); + } } static void test_smbios_memory_size_to_mib(void **state) -- To view, visit https://review.coreboot.org/c/coreboot/+/58601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Gerrit-Change-Number: 58601 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/vilboz: Generate new SPD ID for new memory parts
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58690 ) Change subject: mb/google/zork/var/vilboz: Generate new SPD ID for new memory parts ...................................................................... mb/google/zork/var/vilboz: Generate new SPD ID for new memory parts Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Hynix H5ANAG6NCJR-XNC 2. Micron MT40A512M16TB-062E:R 3. ADATA 4JQA-0622AD BUG=b:199469240 BRANCH=firmware-zork-13434.B TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index f4d0cb4..1e02efa 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -13,3 +13,6 @@ SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E SPD_SOURCES += spd/ddr4/set-0/spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NDMR-XNC SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 8(0b1000) Parts = MT40A1G16RC-062E:B +SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 9(0b1001) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 10(0b1010) Parts = MT40A512M16TB-062E:R +SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 11(0b1011) Parts = 4JQA-0622AD diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt index 4211dab..73f315e 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -11,3 +11,6 @@ MT40A1G16KD-062E:E 6 (0110) H5ANAG6NDMR-XNC 7 (0111) MT40A1G16RC-062E:B 8 (1000) +H5ANAG6NCJR-XNC 9 (1001) +MT40A512M16TB-062E:R 10 (1010) +4JQA-0622AD 11 (1011) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index a4b0aaf..1be55f7 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -14,3 +14,6 @@ MT40A1G16KD-062E:E, 6 H5ANAG6NDMR-XNC, 7 MT40A1G16RC-062E:B, 8 +H5ANAG6NCJR-XNC, 9 +MT40A512M16TB-062E:R, 10 +4JQA-0622AD, 11 -- To view, visit https://review.coreboot.org/c/coreboot/+/58690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e Gerrit-Change-Number: 58690 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/kconfig: Uprev to Linux 5.15's kconfig
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58792 ) Change subject: util/kconfig: Uprev to Linux 5.15's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.15's kconfig Upstream's changes only affect a script that we don't use. Still, this keeps us in sync with the official version. Change-Id: I39cbbfb8dc816b4f36f92e6bd53f40c733691242 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58792 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/kconfig/merge_config.sh 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/kconfig/merge_config.sh b/util/kconfig/merge_config.sh index 63c8565..e5b4698 100755 --- a/util/kconfig/merge_config.sh +++ b/util/kconfig/merge_config.sh @@ -28,6 +28,7 @@ echo " -r list redundant entries when merging fragments" echo " -y make builtin have precedence over modules" echo " -O dir to put generated output files. Consider setting \$KCONFIG_CONFIG instead." + echo " -s strict mode. Fail if the fragment redefines any value." echo echo "Used prefix: '$CONFIG_PREFIX'. You can redefine it with \$CONFIG_ environment variable." } @@ -37,6 +38,7 @@ WARNREDUN=false BUILTIN=false OUTPUT=. +STRICT=false CONFIG_PREFIX=${CONFIG_-CONFIG_} while true; do @@ -75,6 +77,11 @@ shift 2 continue ;; + "-s") + STRICT=true + shift + continue + ;; *) break ;; @@ -141,6 +148,9 @@ echo Previous value: $PREV_VAL echo New value: $NEW_VAL echo + if [ "$STRICT" = "true" ]; then + STRICT_MODE_VIOLATED=true + fi elif [ "$WARNREDUN" = "true" ]; then echo Value of $CFG is redundant by fragment $ORIG_MERGE_FILE: fi @@ -153,6 +163,11 @@ cat $MERGE_FILE >> $TMP_FILE done +if [ "$STRICT_MODE_VIOLATED" = "true" ]; then + echo "The fragment redefined a value and strict mode had been passed." + exit 1 +fi + if [ "$RUNMAKE" = "false" ]; then cp -T -- "$TMP_FILE" "$KCONFIG_CONFIG" echo "#" -- To view, visit https://review.coreboot.org/c/coreboot/+/58792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39cbbfb8dc816b4f36f92e6bd53f40c733691242 Gerrit-Change-Number: 58792 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/kconfig: Uprev to Linux 5.14's kconfig
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57880 ) Change subject: util/kconfig: Uprev to Linux 5.14's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.14's kconfig Upstream's changes have been minimal, to the perl script that we don't use and a constness change, so I expect no harm. Still, this keeps us in sync with the official version. Change-Id: I5e5a2400bc3323938da4b946930e2ec119819672 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57880 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/kconfig/conf.c M util/kconfig/streamline_config.pl 2 files changed, 40 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/kconfig/conf.c b/util/kconfig/conf.c index 803447a..bc7b2f6 100644 --- a/util/kconfig/conf.c +++ b/util/kconfig/conf.c @@ -680,7 +680,7 @@ check_conf(child); } -static struct option long_opts[] = { +static const struct option long_opts[] = { {"help", no_argument, NULL, 'h'}, {"silent", no_argument, NULL, 's'}, {"oldaskconfig", no_argument, &input_mode_opt, oldaskconfig}, diff --git a/util/kconfig/streamline_config.pl b/util/kconfig/streamline_config.pl index 911c72a..1a5fea0 100755 --- a/util/kconfig/streamline_config.pl +++ b/util/kconfig/streamline_config.pl @@ -601,12 +601,12 @@ sub in_preserved_kconfigs { my $kconfig = $config2kfile{$_[0]}; if (!defined($kconfig)) { - return 0; + return 0; } foreach my $excl (@preserved_kconfigs) { - if($kconfig =~ /^$excl/) { - return 1; - } + if($kconfig =~ /^$excl/) { + return 1; + } } return 0; } @@ -629,52 +629,52 @@ } if (/CONFIG_MODULE_SIG_KEY="(.+)"/) { - my $orig_cert = $1; - my $default_cert = "certs/signing_key.pem"; + my $orig_cert = $1; + my $default_cert = "certs/signing_key.pem"; - # Check that the logic in this script still matches the one in Kconfig - if (!defined($depends{"MODULE_SIG_KEY"}) || - $depends{"MODULE_SIG_KEY"} !~ /"\Q$default_cert\E"/) { - print STDERR "WARNING: MODULE_SIG_KEY assertion failure, ", - "update needed to ", __FILE__, " line ", __LINE__, "\n"; - print; - } elsif ($orig_cert ne $default_cert && ! -f $orig_cert) { - print STDERR "Module signature verification enabled but ", - "module signing key \"$orig_cert\" not found. Resetting ", - "signing key to default value.\n"; - print "CONFIG_MODULE_SIG_KEY=\"$default_cert\"\n"; - } else { - print; - } - next; + # Check that the logic in this script still matches the one in Kconfig + if (!defined($depends{"MODULE_SIG_KEY"}) || + $depends{"MODULE_SIG_KEY"} !~ /"\Q$default_cert\E"/) { + print STDERR "WARNING: MODULE_SIG_KEY assertion failure, ", + "update needed to ", __FILE__, " line ", __LINE__, "\n"; + print; + } elsif ($orig_cert ne $default_cert && ! -f $orig_cert) { + print STDERR "Module signature verification enabled but ", + "module signing key \"$orig_cert\" not found. Resetting ", + "signing key to default value.\n"; + print "CONFIG_MODULE_SIG_KEY=\"$default_cert\"\n"; + } else { + print; + } + next; } if (/CONFIG_SYSTEM_TRUSTED_KEYS="(.+)"/) { - my $orig_keys = $1; + my $orig_keys = $1; - if (! -f $orig_keys) { - print STDERR "System keyring enabled but keys \"$orig_keys\" ", - "not found. Resetting keys to default value.\n"; - print "CONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n"; - } else { - print; - } - next; + if (! -f $orig_keys) { + print STDERR "System keyring enabled but keys \"$orig_keys\" ", + "not found. Resetting keys to default value.\n"; + print "CONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n"; + } else { + print; + } + next; } if (/^(CONFIG.*)=(m|y)/) { - if (in_preserved_kconfigs($1)) { - dprint "Preserve config $1"; - print; - next; - } + if (in_preserved_kconfigs($1)) { + dprint "Preserve config $1"; + print; + next; + } if (defined($configs{$1})) { if ($localyesconfig) { - $setconfigs{$1} = 'y'; + $setconfigs{$1} = 'y'; print "$1=y\n"; next; } else { - $setconfigs{$1} = $2; + $setconfigs{$1} = $2; } } elsif ($2 eq "m") { print "# $1 is not set\n"; @@ -702,3 +702,5 @@ print STDERR "\n"; } } + +# vim: softtabstop=4 -- To view, visit https://review.coreboot.org/c/coreboot/+/57880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e5a2400bc3323938da4b946930e2ec119819672 Gerrit-Change-Number: 57880 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/hda: Remove the weak function
by Bao Zheng (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58772 to look at the new patch set (#4). Change subject: amd/hda: Remove the weak function ...................................................................... amd/hda: Remove the weak function BUG=b:140165023 Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/hda/hda.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/58772/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/58772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Gerrit-Change-Number: 58772 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amd/hda: Remove the weak function
by Bao Zheng (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Marshall Dawson, Zheng Bao, Felix Held. Hello Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58772 to look at the new patch set (#3). Change subject: amd/hda: Remove the weak function ...................................................................... amd/hda: Remove the weak function BUG=b:140165023 Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/hda/hda.c M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/58772/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/58772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Gerrit-Change-Number: 58772 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]amd/hda: Remove the weak function
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Marshall Dawson, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58772 ) Change subject: [WIP]amd/hda: Remove the weak function ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/stoneyridge/northbridge.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131988): https://review.coreboot.org/c/coreboot/+/58772/comment/5523e4ac_23ecb5ac PS2, Line 470: /* Look for the hda pci configration define. */ 'configration' may be misspelled - perhaps 'configuration'? -- To view, visit https://review.coreboot.org/c/coreboot/+/58772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Gerrit-Change-Number: 58772 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Nov 2021 08:05:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amd/i2c: Remove the weak function
by Bao Zheng (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Bao Zheng, Raul Rangel, Marshall Dawson, Zheng Bao. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58771 to look at the new patch set (#2). Change subject: amd/i2c: Remove the weak function ...................................................................... amd/i2c: Remove the weak function BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/i2c/i2c.c M src/soc/amd/stoneyridge/i2c.c 2 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/58771/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Gerrit-Change-Number: 58771 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021