coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: Add console deinit API, use in SMM handler
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Nico Huber, Stefan Reinauer, Paul Menzel, Rocky Phagura, Christian Walter, Angel Pons, Arthur Heymans, Kyösti Mälkki, Peter Tsung Ho Wu, Deomid "rojer" Ryabkov, Ron Minnich. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56386 ) Change subject: Add console deinit API, use in SMM handler ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56386/comment/9ff1d452_19ab810c PS11, Line 14: on an OCP Delta Lake server: uart8250_init disables interrupts because it > yes in coreboot stage it's fine, but this change is for entering and exiting smm while printing smm […] So uart8250_init() is called via console_init() in smi_handler() / smm_handler_start() (depending on which SMM modules are used or not). Various things in the handler really should only be called the first time, and console_init belongs in that group IMHO: among other reasons because we don't want to see "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n" emitted on every SMM. (see end of console_init() ) Our serial driver is simple enough that it should cope with most UART reconfiguration the OS might do while not actively using the serial port (in which case SMM should be configured not to interfere with OS talk on that line anyway) +Stefan, do you remember what's going on here? What am I missing? -- To view, visit https://review.coreboot.org/c/coreboot/+/56386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5e51f385f83cb998c244ca1d1ffc10339d3a714 Gerrit-Change-Number: 56386 Gerrit-PatchSet: 11 Gerrit-Owner: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Deomid "rojer" Ryabkov <rojer9(a)fb.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 07:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
by Werner Zeh (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58740 ) Change subject: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58740/comment/4b3377e2_a5130ed5 PS3, Line 18: and > on? No, 'and' is what I really mean here. These are two features: CLKREQ in terms of Clock-Request via the dedicated pin where the PCIe clock can be switched off when not needed and the CLK-Output itself where the PCIe clock is driven from the chipset and unused clock outputs are disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/58740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Gerrit-Change-Number: 58740 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 06:52:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/kconfig: Rewrite patch in quilt's normal form
by Patrick Georgi (Code Review) 02 Nov '21

02 Nov '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57878 ) Change subject: util/kconfig: Rewrite patch in quilt's normal form ...................................................................... util/kconfig: Rewrite patch in quilt's normal form This is what quilt writes on `quilt refresh` and what it can apply and unapply cleanly. Change-Id: I8c8586da384b65fd5c21c1c1a093642534f83283 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57878 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch 1 file changed, 5 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch b/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch index 8442349..931169d 100644 --- a/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch +++ b/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch @@ -9,11 +9,11 @@ util/kconfig/mconf-cfg.sh | 6 ++++++ 1 file changed, 6 insertions(+) -diff --git a/util/kconfig/mconf-cfg.sh b/util/kconfig/mconf-cfg.sh -index b520e407a8..2047e626b4 100755 ---- a/util/kconfig/mconf-cfg.sh -+++ b/util/kconfig/mconf-cfg.sh -@@ -33,6 +33,12 @@ if [ -f /usr/include/ncurses/ncurses.h ]; then +Index: kconfig/mconf-cfg.sh +=================================================================== +--- kconfig.orig/mconf-cfg.sh ++++ kconfig/mconf-cfg.sh +@@ -33,6 +33,12 @@ if [ -f /usr/include/ncurses/ncurses.h ] exit 0 fi @@ -26,6 +26,3 @@ # As a final fallback before giving up, check if $HOSTCC knows of a default # ncurses installation (e.g. from a vendor-specific sysroot). if echo '#include <ncurses.h>' | ${HOSTCC} -E - >/dev/null 2>&1; then --- -2.31.1 - -- To view, visit https://review.coreboot.org/c/coreboot/+/57878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c8586da384b65fd5c21c1c1a093642534f83283 Gerrit-Change-Number: 57878 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58740 ) Change subject: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58740/comment/3992e0cb_de6c8829 PS3, Line 18: and on? -- To view, visit https://review.coreboot.org/c/coreboot/+/58740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Gerrit-Change-Number: 58740 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 06:34:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO drivers
by build bot (Jenkins) (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58836 ) Change subject: soc/mediatek/mt8186: Add GPIO drivers ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8186/include/soc/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131973): https://review.coreboot.org/c/coreboot/+/58836/comment/70552f37_150414ae PS2, Line 21: #define PIN(id, name, flag, bit, base, offset, \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/58836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Gerrit-Change-Number: 58836 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 06:33:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
by Mario Scheithauer (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58568 ) Change subject: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Gerrit-Change-Number: 58568 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 06:31:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ChromeOS: Remove separate gnvs.asl
by Kyösti Mälkki (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58421 to look at the new patch set (#2). Change subject: ChromeOS: Remove separate gnvs.asl ...................................................................... ChromeOS: Remove separate gnvs.asl The allocation is no longer GNVS but was renamed to CNVS and it is not globally available for ASL. Change-Id: I449d0206fbaee94cea99f745cf297ad293e8306c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/google/chromeos/acpi/chromeos.asl D src/vendorcode/google/chromeos/acpi/gnvs.asl 2 files changed, 27 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/58421/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I449d0206fbaee94cea99f745cf297ad293e8306c Gerrit-Change-Number: 58421 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ChromeOS: Create pseudo-device ACPI NVS
by Kyösti Mälkki (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Nick Vaccaro, Julius Werner, Kyösti Mälkki, Felix Held. Hello Lance Zhao, build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Julius Werner, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55502 to look at the new patch set (#9). Change subject: ChromeOS: Create pseudo-device ACPI NVS ...................................................................... ChromeOS: Create pseudo-device ACPI NVS Treate allocation and initialisation of ChromeOS related NVS as a device and move related calls into device-model. Move the CNVS OperationRegion from \CNVS to \CRHW.CNVS with local scope reference. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/acpi/acpigen_extern.asl M src/acpi/dsdt_top.asl M src/include/acpi/acpi.h M src/lib/hardwaremain.c M src/mainboard/amd/majolica/mainboard.c M src/mainboard/google/auron/mainboard.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/brya/mainboard.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/cyan/mainboard.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/deltaur/mainboard.c M src/mainboard/google/drallion/ramstage.c M src/mainboard/google/eve/mainboard.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/glados/mainboard.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/jecht/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/poppy/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/sarien/ramstage.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/zork/mainboard.c M src/mainboard/intel/adlrvp/mainboard.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/coffeelake_rvp/mainboard.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/glkrvp/mainboard.c M src/mainboard/intel/icelake_rvp/mainboard.c M src/mainboard/intel/jasperlake_rvp/mainboard.c M src/mainboard/intel/kblrvp/mainboard.c M src/mainboard/intel/kunimitsu/mainboard.c M src/mainboard/intel/shadowmountain/mainboard.c M src/mainboard/intel/strago/mainboard.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/samsung/stumpy/mainboard.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/acpi/chromeos.asl M src/vendorcode/google/chromeos/acpi/gnvs.asl M src/vendorcode/google/chromeos/acpi/ramoops.asl M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 54 files changed, 51 insertions(+), 153 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/55502/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/55502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Gerrit-Change-Number: 55502 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 ) Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: I added support for a few more die densities (now 4, 6, 8, 12, 16, 24, 32 Gb). I initially limited it to 8, 12, 16 since these are the ones included in the advisory, but I don't think there's any reason not to support more. I also decided it was clearer to encode the row address bits in two stages: density -> row address bits, then row address bits -> SPD encoding. -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 7 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Nov 2021 06:25:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/spd_tools: Add LP5 support for ADL
by Reka Norman (Code Review) 02 Nov '21

02 Nov '21

Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Hello build bot (Jenkins), Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58679 to look at the new patch set (#7). Change subject: util/spd_tools: Add LP5 support for ADL ...................................................................... util/spd_tools: Add LP5 support for ADL Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman(a)google.com> --- M util/spd_tools/src/part_id_gen/part_id_gen.go A util/spd_tools/src/spd_gen/lp5.go M util/spd_tools/src/spd_gen/spd_gen.go 3 files changed, 629 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/58679/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Gerrit-Change-Number: 58679 Gerrit-PatchSet: 7 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021