coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek/mt8195: fix apusys coding defects
by Yu-Ping Wu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, flora.fu(a)mediatek.com. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59038 ) Change subject: soc/mediatek/mt8195: fix apusys coding defects ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic03f71b7a9038edb5877ebd9b6aed5e9bd63c918 Gerrit-Change-Number: 59038 Gerrit-PatchSet: 2 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 01:30:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Hello Bora Guvendik, build bot (Jenkins), Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58351 to look at the new patch set (#10). Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... soc/intel/common: add generic gpio lock mechanism For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 154 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B
by Reka Norman (Code Review) 10 Nov '21

10 Nov '21

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59006 ) Change subject: mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59006/comment/a9cce1f0_a637c8f9 PS2, Line 10: copied to CSE_RW, so the sizes of these regions need to match. > Why take the smaller value of the two? SI_ME is at least 1M larger than necessary. When Furquan added the sub-regions to SI_ME in CB:58592, I assume he just allocated the extra space to CSE_RW because it's at the end, then increased ME_RW_A/B to match because there's plenty of space in RW_A/B. But there's no reason for any of these regions to be larger than 3M. -- To view, visit https://review.coreboot.org/c/coreboot/+/59006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2 Gerrit-Change-Number: 59006 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 01:25:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5
by Subrata Banik (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Maulik V Vaghela, Ravishankar Sarawadi, Tim Wawrzynczak, Reka Norman, Meera Ravindranath, Nick Vaccaro, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52731 ) Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5 ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/52731/comment/9df55551_d2fdb8b6 PS7, Line 10: { 0, 1 }, : { 2, 2 }, : { 3, 47 }, : { 126, 127 }, : { 192, 213 }, : { 230, 235 }, : { 512, 520 }, : { 521, 550 }, > Do you know where the JEDEC documentation for the changes added to the SPD table values are for DDR5 […] SPD5118, SPD5108 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARD JESD300-5 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/52731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 01:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: Remove unused spinlock functions
by Kyösti Mälkki (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Nico Huber, Marshall Dawson, Julius Werner, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59020 ) Change subject: treewide: Remove unused spinlock functions ...................................................................... Patch Set 2: Code-Review-1 (2 comments) Patchset: PS2: Not addressing the rootcause of CONFIG(SMP) evaluating incorrectly for psp_verstagte, fixing of which would remove the entire file this touches psp_verstage ... smp/spinlock.h. If you ask me, spin_lock() should only do the spinlock and solution to co-operative multitasking might want the functions removed here. There's really no harm that they exist in the header? File src/soc/amd/common/psp_verstage/include/arch/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/59020/comment/985fa454_1a22b402 PS2, Line 8: #define spin_unlock(lock) do {} while (0) > Just FYI, the following diff allows the psp_verstage spinlock.h to be removed: […] Thanks. You need the config with CMOS_POST=y apparently to make it fail. -- To view, visit https://review.coreboot.org/c/coreboot/+/59020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9a742e6b311d972a260039401bfd8f8766dd36 Gerrit-Change-Number: 59020 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 01:11:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTONLY] Generate the SPD for a LP5 test part
by Reka Norman (Code Review) 10 Nov '21

10 Nov '21

Reka Norman has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/58680 ) Change subject: [TESTONLY] Generate the SPD for a LP5 test part ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/58680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96399c17577b1350c6e04c87cf40c4b2ff1478e Gerrit-Change-Number: 58680 Gerrit-PatchSet: 10 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Martin Roth (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Mario Scheithauer, Lean Sheng Tan, Werner Zeh, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 52: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55367/comment/0fa1fcbb_f57ff5e4 PS52, Line 9: The Intel® Programmable Services Engine (Intel® PSE) is a : dedicated offload engine for IoT functions powered by an ARM : Cortex-M7 microcontroller. It provides independent, low-DMIPS : computing and low-speed I/Os for IoT applications, plus : dedicated services for real-time computing and time-sensitive : synchronization. : : The PSE hosts new functions, including remote out-of-band : device management, network proxy, embedded controller lite : and sensor hub. : : This CL enables the user to provide the base address of the : PSE FW blob which will then be loaded by the FSP-S onto the : ARM controller. PSE FW will do the initialization work of : PSE controller and it's peripherals. The loading of PSE FW : should have negligible impact on boot time unless PSE : controller could not locate PSE FW and FSP will attempt to : redo PSE FW loading and wait for PSE handshake until it times : out. Once PSE controller locate PSE FW, it will do initialization : concurrently by itself with coreboot booting. : : It also adds PSE related FSP-S UPD settings which enables the : setup of peripheral ownership (assigned to the PSE or x86 : subsystem) and interrupts. These assignments need to take : place at a given point in the boot process and cannot be : changed later. : : To verify if PSE FW is loaded properly, the user could enable : PchPseShellEnabled flag and the log will be printed at PSE UART 2. : : For further info please refer to doc #611825 (for HW overview) : and #614110 (for PSE EDS). > Isn't the limit 72 characters per line? Yes, 72 characters is the preferred length. https://doc.coreboot.org/getting_started/writing_documentation.html#basic-a… File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/582e7ec8_16318701 PS2, Line 58: pse.bin-align := 0x1000 > Looks like FSP copies the PSE FW to RAM, so the alignment of the file in CBFS shouldn't matter. […] I agree with Angel here. Adding an artificial alignment requirement will tend to waste space in CBFS. It's not a big deal, but since it's actually being decompressed, I don't see any reason for the alignment requirement. Maybe at one point it wasn't being compressed and was being loaded directly from the rom space? -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 52 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 01:04:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Hello Bora Guvendik, build bot (Jenkins), Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58351 to look at the new patch set (#9). Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... soc/intel/common: add generic gpio lock mechanism For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 154 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7280: gpio: Support eGPIO scheme
by Taniya Das (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58580 ) Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme ...................................................................... Patch Set 4: (4 comments) File src/soc/qualcomm/common/gpio.c: https://review.coreboot.org/c/coreboot/+/58580/comment/564af3c3_055f0f2b PS2, Line 21: if ((read32(&regs->cfg) >> GPIO_EGPIO_SHFT) & GPIO_EGPIO_BMSK) > Seem like we can just add it to the condition above. Something like: […] I might be missing something here, but we want to set the 12th bit only in case the 11th bit (eGPIO_PRESENT) is set. File src/soc/qualcomm/common/include/soc/gpio_common.h: https://review.coreboot.org/c/coreboot/+/58580/comment/8eaa4135_c28dff90 PS2, Line 24: GPIO_EGPIO_BMSK > GPIO_CFG_EGPIO_BMSK? Done https://review.coreboot.org/c/coreboot/+/58580/comment/e50f16ee_c1cd183d PS2, Line 39: GPIO_EGPIO_SHFT > GPIO_CFG_EGPIO_SHFT? Done https://review.coreboot.org/c/coreboot/+/58580/comment/d5b93369_caa4d319 PS2, Line 87: enum egpio_cfg { > Is the plan to add more fields in here in the future? Just curious why we have an enum for 1 type. Yes, we might need to add more fields in future, thus added the enum. -- To view, visit https://review.coreboot.org/c/coreboot/+/58580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 Gerrit-Change-Number: 58580 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 00:49:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Hello Bora Guvendik, build bot (Jenkins), Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58351 to look at the new patch set (#8). Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... soc/intel/common: add generic gpio lock mechanism For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 157 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58351/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021