coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/primus: Disable autonomous GPIO power management
by Casper Chang (Code Review) 10 Nov '21

10 Nov '21

Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59079 ) Change subject: mb/google/brya/var/primus: Disable autonomous GPIO power management ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59079/comment/f7a2b2d3_c77aba7a PS2, Line 7: disabled > `Disable` Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Gerrit-Change-Number: 59079 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 03:40:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus: Disable autonomous GPIO power management
by Casper Chang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Casper Chang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59079 to look at the new patch set (#3). Change subject: mb/google/brya/var/primus: Disable autonomous GPIO power management ...................................................................... mb/google/brya/var/primus: Disable autonomous GPIO power management Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/primus/overridetree.cb 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59079/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Gerrit-Change-Number: 59079 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Add APCB combo
by build bot (Jenkins) (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58620 ) Change subject: amdfwtool: Add APCB combo ...................................................................... Patch Set 9: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132784): https://review.coreboot.org/c/coreboot/+/58620/comment/d7ab46a6_2dfe6ef6 PS9, Line 1637: combo_apcb_bk[combo_index].ins & 0xF, combo_apcb_bk[combo_index].filename); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/58620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c2bf7d98ded43848ae8a8bb61d1ded1a277f88 Gerrit-Change-Number: 58620 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 10 Nov 2021 03:35:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Create/fill the combo header and write to EFS header
by build bot (Jenkins) (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55412 ) Change subject: amdfwtool: Create/fill the combo header and write to EFS header ...................................................................... Patch Set 24: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132782): https://review.coreboot.org/c/coreboot/+/55412/comment/0e3eabcc_6979509d PS24, Line 1244: psp_combo_directory *psp_combo_dir = NULL, *bhd_combo_dir = NULL; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/55412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3d831c7764ac4625b336d40e09bb308d339f7b Gerrit-Change-Number: 55412 Gerrit-PatchSet: 24 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 10 Nov 2021 03:34:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Move PSP padding into a loop for combo
by build bot (Jenkins) (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58554 ) Change subject: amdfwtool: Move PSP padding into a loop for combo ...................................................................... Patch Set 17: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132783): https://review.coreboot.org/c/coreboot/+/58554/comment/f4cced62_96d90d58 PS17, Line 1571: do { suspect code indent for conditional statements (8, 8) -- To view, visit https://review.coreboot.org/c/coreboot/+/58554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I351192a4bc5ed9ec0bfa3f2073c9633b8b44246d Gerrit-Change-Number: 58554 Gerrit-PatchSet: 17 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 10 Nov 2021 03:34:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Create/fill the combo header and write to EFS header
by Bao Zheng (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55412 to look at the new patch set (#24). Change subject: amdfwtool: Create/fill the combo header and write to EFS header ...................................................................... amdfwtool: Create/fill the combo header and write to EFS header Now the COMBO header for one entry is implemented. Change-Id: I4e3d831c7764ac4625b336d40e09bb308d339f7b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 69 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/55412/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/55412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3d831c7764ac4625b336d40e09bb308d339f7b Gerrit-Change-Number: 55412 Gerrit-PatchSet: 24 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Kevin Chiu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Karthik Ramasubramanian. Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59053 ) Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/guybrush/variants/nipperkin/gpio.c: https://review.coreboot.org/c/coreboot/+/59053/comment/a299f5ca_1dcfae15 PS2, Line 51: PAD_NC(GPIO_69), > Can be removed as well and then bid1_override_pcie_gpio_table can be consolidated with bid2_override […] this needs to be removed since nipperkin board version 2 uses GPIO69 as SD AUX RESET too, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 03:18:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable CPU PCIE RP 1
by Joey Peng (Code Review) 10 Nov '21

10 Nov '21

Joey Peng has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/59080 ) Change subject: mb/google/brya/var/taeko: Enable CPU PCIE RP 1 ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/59080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Gerrit-Change-Number: 59080 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Update SPKR GPIO configuration
by Kevin Chiu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Bhanu Prakash Maiya, Rob Barnes, Eric Peers, Karthik Ramasubramanian. Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59051 ) Change subject: mb/google/guybrush/var/nipperkin: Update SPKR GPIO configuration ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59051/comment/9c56187a_b6040ec5 PS2, Line 12: SD_AUX_RESET_L: GPIO69 > Agree. I'll update with CL in a moment. remove SD AUX RESET, thanks. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Gerrit-Change-Number: 59051 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 03:11:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable CPU PCIE RP 1
by Joey Peng (Code Review) 10 Nov '21

10 Nov '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59080 ) Change subject: mb/google/brya/var/taeko: Enable CPU PCIE RP 1 ...................................................................... mb/google/brya/var/taeko: Enable CPU PCIE RP 1 Modify settings to enable CPU PCIE RP 1 according to schematics. BUG=b:205504257 TEST=emerge-brya coreboot and can successfully boot with ssd and emmc. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 --- M src/mainboard/google/brya/variants/taeko/gpio.c M src/mainboard/google/brya/variants/taeko/overridetree.cb 2 files changed, 31 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/59080/1 diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index b67cc49..7ef9868 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -47,8 +47,8 @@ /* D3 : ISH_GP3 ==> NC */ PAD_NC(GPP_D3, NONE), - /* D5 : SRCCLKREQ0# ==> NC */ - PAD_NC(GPP_D5, NONE), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> NC */ PAD_NC(GPP_D9, NONE), /* D10 : ISH_SPI_CLK ==> NC */ @@ -175,6 +175,28 @@ * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. */ PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 8ad5479..d6d7c9b 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -221,6 +221,13 @@ device generic 0 alias dptf_policy on end end end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" + end device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp2 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/59080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Gerrit-Change-Number: 59080 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021