coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Varshit B Pandya (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/58767/comment/95039cc3_d3c80faa PS7, Line 851: acpi_dsc > `max_dstate_for_probe` […] how about dstate_during_kernel_probe ? or will it be too long ? -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 7 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:24:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Use command line option combo to decide if use combo
by Bao Zheng (Code Review) 10 Nov '21

10 Nov '21

Bao Zheng has restored this change. ( https://review.coreboot.org/c/coreboot/+/55455 ) Change subject: amdfwtool: Use command line option combo to decide if use combo ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/55455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Gerrit-Change-Number: 55455 Gerrit-PatchSet: 18 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: restore

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs
by Tracy Wu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Patrick Rudolph, EricR Lai. Tracy Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/pcie/pcie.c: https://review.coreboot.org/c/coreboot/+/59081/comment/05d5eab9_05592b76 PS1, Line 316: PCIE > PEG, so won't confuse with PCIE port Hi Eric, This is more formal name of PEG port For PCH pcie port, we use "ADP" (PCH processor) For CPU we use with CPU processor Thanks, Tracy -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 1 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:21:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Get vb2_context early
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59017 ) Change subject: soc/amd/psp_verstage: Get vb2_context early ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/59017/comment/db2ceb00_d7adc325 PS1, Line 224: > IMO vbnv_init(ctx->nvdata) should be added here since reboot_into_recovery calls vb2api_fail and vbo […] Turns out, vbnv_init(ctx->nvdata) fails here because the cmos isn't ready until after verstage_soc_early_init/map_fch_devices. This also means reboot_into_recovery will fail here too. So the below error logic only works if verstage_soc_early_init mostly succeeds and cmos is accessible. This CL does not fix the bug completely, but it doesn't make worse either. If there's a fatal error and the cmos is not accessible, is there a viable recovery path? -- To view, visit https://review.coreboot.org/c/coreboot/+/59017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Gerrit-Change-Number: 59017 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs
by EricR Lai (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tracy Wu, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/pcie/pcie.c: https://review.coreboot.org/c/coreboot/+/59081/comment/0f8060e9_3cf9e85b PS1, Line 316: PCIE PEG, so won't confuse with PCIE port -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 1 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:07:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH
by David Wu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59035 ) Change subject: mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59035/comment/088e3b54_50580eb5 PS2, Line 7: register "pmc_gpe0_dw1" = "GPP_D" > I think it would be better to override this setting in kano's overridetree instead of the baseboard, […] Done. Thanks for your reminder. -- To view, visit https://review.coreboot.org/c/coreboot/+/59035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b Gerrit-Change-Number: 59035 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:02:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH
by David Wu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: David Wu, Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59035 to look at the new patch set (#3). Change subject: mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH ...................................................................... mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:192415743 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/kano/gpio.c M src/mainboard/google/brya/variants/kano/overridetree.cb 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/59035/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b Gerrit-Change-Number: 59035 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs
by Tracy Wu (Code Review) 10 Nov '21

10 Nov '21

Tracy Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs ...................................................................... soc/intel/common/block/pcie: Add ADL-P PEG Device IDs List of changes: 1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h 2. Add these new PEG IDs into pcie_device_ids[] in pcie.c BUG=b:205668996 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59081/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1ed6ac9..c6ef121 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3332,6 +3332,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1 0x464d +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2 0x460d +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3 0x463d + #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1 0x51b8 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2 0x51b9 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3 0x51ba diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 6d3d6ab..0c3e225 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -313,6 +313,9 @@ PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7, PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3, PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1, PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2, PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3, -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 1 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Add support for PCI MMIO CONFIG access.
by Prasad Malisetty (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Shelley Chen, Ravi kumar, Furquan Shaikh, Arthur Heymans. Prasad Malisetty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57615 ) Change subject: libpayload: Add support for PCI MMIO CONFIG access. ...................................................................... Patch Set 18: (2 comments) Patchset: PS17: > Hi Prasad, I've created a CL with proposed code changes for the libpayload MMIO ops for PCI CONFIG s […] Hi Shelley, Thanks for the update. I have acknowledged your comments. I will update new patch series with addressing all comments. Thanks -Prasad File payloads/libpayload/drivers/pci_ops.c: https://review.coreboot.org/c/coreboot/+/57615/comment/beaad023_278764d3 PS17, Line 34: uintptr_t get_pci_mmio_cfgbase(pcidev_t dev) > This only works if you have one device, correct? Would it be possible to port the coreboot atu mapp […] ATU configuration needed for every config/mem read/write. ATU configuration function is in coreboot PCIe driver. I am not really how we can call coreboot functions from payloads. Could you please help if we have that infra. Thanks -Prasad -- To view, visit https://review.coreboot.org/c/coreboot/+/57615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Gerrit-Change-Number: 57615 Gerrit-PatchSet: 18 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 10 Nov 2021 03:48:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Export PCIe MMCONF from coreboot to libpayload
by Prasad Malisetty (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Arthur Heymans, Furquan Shaikh, Kyösti Mälkki. Prasad Malisetty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57614 ) Change subject: libpayload: Export PCIe MMCONF from coreboot to libpayload ...................................................................... Patch Set 18: (3 comments) Patchset: PS16: > Hi Prasad, can we use MMIO instead of MMCONF (throughout this whole CL)? In coreboot, we've agreed […] Hi Shelley, Thanks for the review. I will replace MMCONF with MMIO in next patch series. -Prasad File payloads/libpayload/include/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/57614/comment/4773010c_21709d57 PS12, Line 275: void *mmconf_base; > Hi Arthur, […] Sure, I will share the updated change set File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/57614/comment/c1639dac_63e5e57f PS8, Line 500: if PCI > Agreed that this should not be moved. Hi Arthur, I was getting some conflict between ARM and X86 version pci.c lib. I agree on it. I will correct it and incorporate the change in next patch version. Thanks -Prasad -- To view, visit https://review.coreboot.org/c/coreboot/+/57614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940 Gerrit-Change-Number: 57614 Gerrit-PatchSet: 18 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 03:42:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021