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Change subject: mb/google/brya/var/primus: disabled autonomous GPIO power management
......................................................................
mb/google/brya/var/primus: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59079/2
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Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59079 )
Change subject: mb/google/brya/var/primus: disabled autonomous GPIO power management
......................................................................
mb/google/brya/var/primus: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/59079/1
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index c4debb4..81dc1c0 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -22,7 +22,16 @@
end
chip soc/intel/alderlake
-
+ # This disabled autonomous GPIO power management, otherwise
+ # old cr50 FW only supports short pulses; need to clarify
+ # the minimum PCH IRQ pulse width with Intel, b/180111628
+ register "gpio_override_pm" = "1"
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
+ register "gpio_pm[COMM_4]" = "0"
+ register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
register "MaxDramSpeed" = "3733"
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 )
Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 32:
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132771):
https://review.coreboot.org/c/coreboot/+/57131/comment/c2678dcf_a21d9f01
PS32, Line 1848: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER);
line over 96 characters
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Change subject: amdfwtool: Pack out-of-bounds check into a function and move
......................................................................
Patch Set 5:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/58764/comment/4aed4b9d_341e904b
PS4, Line 737:
> since the count variable might get incremented in the if/else construct above, another assert_fw_ent […]
Done
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David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59035 )
Change subject: mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/kano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59035/comment/6dff4ab3_ed826f7b
PS1, Line 230: register "key.wake_gpe" = "GPE0_DW1_17"
> The baseboard has defined the three GPE0_DW* groups as: […]
Done. Thanks.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56773
to look at the new patch set (#32).
Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
M util/amdfwtool/data_parse.c
3 files changed, 184 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56773/32
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Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Pack out-of-bounds check into a function and move
......................................................................
amdfwtool: Pack out-of-bounds check into a function and move
Need to check the FWs number limit several times. So pack the
duplicated steps into a function. And do it before access the new
entry.
Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 15 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/58764/5
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH
......................................................................
mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
BUG=b:192415743
TEST=build pass
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/brya/variants/kano/gpio.c
M src/mainboard/google/brya/variants/kano/overridetree.cb
4 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/59035/2
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58969 )
Change subject: soc/mediatek/mt8195: Add APU device apc driver
......................................................................
Patch Set 8:
(2 comments)
File src/soc/mediatek/mt8195/apusys_devapc.c:
https://review.coreboot.org/c/coreboot/+/58969/comment/1c1d319c_be87f970
PS6, Line 196: ARRAY_SIZE(apusys_noc_dapc)
> Yes, but the APUSYS_NOC_DAPC_AO_SLAVE_NUM is used to do runtime checking when setting devapc registe […]
Then can we check the values are the same somewhere?
_Static_assert(ARRAY_SIZE(apusys_noc_dapc), APUSYS_NOC_DAPC_AO_SLAVE_NUM);
File src/soc/mediatek/mt8195/apusys_devapc.c:
https://review.coreboot.org/c/coreboot/+/58969/comment/3f1ab538_38d20912
PS8, Line 237:
Also print i? Same below.
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Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59006 )
Change subject: mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59006/comment/1d2e25ca_18f77a11
PS2, Line 10: copied to CSE_RW, so the sizes of these regions need to match.
> SI_ME is at least 1M larger than necessary. […]
Actually that's not quite right, sorry. There's about 0.5M free when you include the SI_EC region which was added back in CB:58661 (which is what triggered this change).
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