coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/common/psp_verstage: Remove confusing boot_cpu()
by Kyösti Mälkki (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59069 ) Change subject: soc/amd/common/psp_verstage: Remove confusing boot_cpu() ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: Not addressing the rootcause of CONFIG(SMP) evaluating incorrectly for psp_verstagte, fixing of which would remove the entire file this touches. -- To view, visit https://review.coreboot.org/c/coreboot/+/59069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4e0604b37f036dcf07debbd8d796d7a493dbd30 Gerrit-Change-Number: 59069 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 00:35:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/58351/comment/e93d4523_29c5ef3a PS7, Line 461: int gpio_lock_multiple_pads(const struct gpio_lock_config *pads_a, const size_t count_a, : const struct gpio_lock_config *pads_b, const size_t count_b) > this is kind of an awkward API to use... […] I had thought about that as well, seems much more straight-foward to have the routine support locking a single list. However, I would suggest just calling it twice (once for each list, or if only one list exists, it will only get called once) instead of the malloc - catenate lists - free approach. I *think* the overhead would be less and make for a simpler approach. Thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 7 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 00:18:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,picasso/include/southbridge: use bitwise or in defines
by Felix Held (Code Review) 10 Nov '21

10 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59030 ) Change subject: soc/amd/cezanne,picasso/include/southbridge: use bitwise or in defines ...................................................................... soc/amd/cezanne,picasso/include/southbridge: use bitwise or in defines Use bitwise or instead of additions to build bit masks with multiple bits set. TEST=Timeless build results in identical image on amd/mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/southbridge.h 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 1e3697b..b492088 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -99,15 +99,15 @@ #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 #define MISC_I2C3_PAD_CTRL 0xe4 -#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3)) +#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5)) +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) #define I2C_PAD_CTRL_RX_SHIFT 4 #define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) #define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) #define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) #define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) #define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 #define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) #define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 300f458..2936600 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -96,15 +96,15 @@ #define MISC_I2C1_PAD_CTRL 0xdc #define MISC_I2C2_PAD_CTRL 0xe0 #define MISC_I2C3_PAD_CTRL 0xe4 -#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3)) +#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) #define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5)) +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) #define I2C_PAD_CTRL_RX_SHIFT 4 #define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) #define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) #define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) #define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) #define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 #define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) #define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -- To view, visit https://review.coreboot.org/c/coreboot/+/59030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Gerrit-Change-Number: 59030 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update typeC EC mux port
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: EricR Lai. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59012 ) Change subject: mb/google/brya/var/felwinter: Update typeC EC mux port ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > let's give this a think and see if there's a better way to do this, so we don't have to correctly or […] +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Gerrit-Change-Number: 59012 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 00:08:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Spell Intel Cooper Lake-SP with a space
by Felix Singer (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Christian Walter, Arthur Heymans, Patrick Rudolph, Tim Chu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59036 ) Change subject: Spell Intel Cooper Lake-SP with a space ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Gerrit-Change-Number: 59036 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 00:03:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Document adding support for a new memory technology
by Tim Wawrzynczak (Code Review) 10 Nov '21

10 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59005 ) Change subject: util/spd_tools: Document adding support for a new memory technology ...................................................................... util/spd_tools: Document adding support for a new memory technology Add documentation describing how to add support for a new memory technology to spd_tools: - Add a section to the README. - Document the memTech interface in spd_gen.go. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/spd_tools/README.md M util/spd_tools/src/spd_gen/spd_gen.go 2 files changed, 72 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/util/spd_tools/README.md b/util/spd_tools/README.md index a422017..3a1342c 100644 --- a/util/spd_tools/README.md +++ b/util/spd_tools/README.md @@ -590,3 +590,48 @@ `dram_id.generated.txt` with the new part. * Upload the changes to `Makefile.inc` and `dram_id.generated.txt` for review. + +## How to add support for a new memory technology + +### 1. Gather the SPD requirements + +To generate SPDs for the new memory technology, information is needed about the +list of bytes in the SPD and how the value of each byte should be determined. +This information usually comes from a combination of: + +* The JEDEC spec for the memory technology, e.g. JESD209-5B for LPDDR5. +* The JEDEC SPD spec for the memory technology, e.g. SPD4.1.2.M-2 for LPDDR3/4 + (also used for LP4x and LP5). +* Platform-specific requirements. SoC vendors often don't follow the JEDEC + specs exactly. E.g. the memory training code may expect certain SPD bytes to + encode a different value to what is stated in the spec. So for each SoC + platform using the new memory technology, any platform-specific requirements + need to be gathered. + +### 2. Implement support in spd_tools + +Support for the new memory technology needs to be added to both the `spd_gen` +and `part_id_gen` tools. + +#### `spd_gen` + +Adding support to `spd_gen` requires implementing the logic to generate SPDs for +the new memory technology. The changes required are: + +* Add the new memory technology to the `memTechMap` in `spd_gen/spd_gen.go`. +* Add a new file `spd_gen/<mem_tech>.go`. This file will contain all the logic + for generating SPDs for the new memory technology. It needs to implement the + `memTech` interface defined in `spd_gen/spd_gen.go`. The interface functions + are documented inline. Examples of how the interface is implemented for + existing memory technologies can be found in the `spd_gen/` directory, e.g. + `lp4x.go`, `ddr4.go`, `lp5.go`. While not strictly necessary, it is + recommended to follow the overall structure of these existing files when + adding a new memory technology. + +#### `part_id_gen` + +The `part_id_gen` tool is memory technology-agnostic, so the only change +required is: + +* Add the new memory technology to the `supportedMemTechs` list in + `part_id_gen/part_id_gen.go`. diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go index fa65492..6cc9102 100644 --- a/util/spd_tools/src/spd_gen/spd_gen.go +++ b/util/spd_tools/src/spd_gen/spd_gen.go @@ -28,10 +28,37 @@ } type memTech interface { + /* + * Returns the set -> platform mapping for the memory technology. Platforms with the + * same SPD requirements should be grouped together into a single set. + */ getSetMap() map[int][]int + + /* + * Takes the name and attributes of a part, as read from the memory_parts JSON file. + * Validates the attributes, returning an error if any attribute has an invalid value. + * Stores the name and attributes internally to be used later. + */ addNewPart(string, interface{}) error + + /* + * Takes the name of a part and a set number. + * Retrieves the part's attributes which were stored by addNewPart(). Updates them by + * setting any optional attributes which weren't specified in the JSON file to their + * default values. + * Returns these updated attributes. + */ getSPDAttribs(string, int) (interface{}, error) + + /* + * Returns the size of an SPD file for this memory technology. + */ getSPDLen() int + + /* + * Takes an SPD byte index and the attributes of a part. + * Returns the value which that SPD byte should be set to based on the attributes. + */ getSPDByte(int, interface{}) byte } -- To view, visit https://review.coreboot.org/c/coreboot/+/59005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305 Gerrit-Change-Number: 59005 Gerrit-PatchSet: 6 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Maulik V Vaghela, Ravishankar Sarawadi, Tim Wawrzynczak, Reka Norman, Meera Ravindranath, Balaji Manigandan, Raj Astekar, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52731 ) Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5 ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/52731/comment/29cf89eb_281f2977 PS7, Line 10: { 0, 1 }, : { 2, 2 }, : { 3, 47 }, : { 126, 127 }, : { 192, 213 }, : { 230, 235 }, : { 512, 520 }, : { 521, 550 }, > I would really like to see symbolic constants (and possibly comments) here defining what each of the […] Do you know where the JEDEC documentation for the changes added to the SPD table values are for DDR5 (eg. new constant for DDR5 memory type, etc). I didn't see that information in the JESD79-5A spec. Am I overlooknig it? -- To view, visit https://review.coreboot.org/c/coreboot/+/52731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 09 Nov 2021 23:45:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Document adding support for a new memory technology
by Tim Wawrzynczak (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Reka Norman, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59005 ) Change subject: util/spd_tools: Document adding support for a new memory technology ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305 Gerrit-Change-Number: 59005 Gerrit-PatchSet: 5 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Nov 2021 23:44:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/fsp_m_parameters: add curly braces around else block
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59070 ) Change subject: soc/amd/cezanne/fsp_m_parameters: add curly braces around else block ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475 Gerrit-Change-Number: 59070 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Nov 2021 23:23:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne,picasso/include/southbridge: fix typo in define
by Felix Held (Code Review) 10 Nov '21

10 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59028 ) Change subject: soc/amd/cezanne,picasso/include/southbridge: fix typo in define ...................................................................... soc/amd/cezanne,picasso/include/southbridge: fix typo in define In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/southbridge.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index addb850..1e3697b 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -118,7 +118,7 @@ #define I2C_PAD_CTRL_CAP_UP BIT(13) #define I2C_PAD_CTRL_RES_DOWN BIT(14) #define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index f547f86..300f458 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -115,7 +115,7 @@ #define I2C_PAD_CTRL_CAP_UP BIT(13) #define I2C_PAD_CTRL_RES_DOWN BIT(14) #define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -- To view, visit https://review.coreboot.org/c/coreboot/+/59028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Gerrit-Change-Number: 59028 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021