coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs
by EricR Lai (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tracy Wu, Kane Chen, Tim Wawrzynczak, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 1 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:52:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Kevin Chiu, Raul Rangel, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59053 ) Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/guybrush/variants/guybrush/gpio.c: https://review.coreboot.org/c/coreboot/+/59053/comment/f59318be_9d5ba4fc PS2, Line 57: /* This table is used by guybrush variant with board version >= 2. */ : static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { : }; : > Nit: Empty table can be removed and NULL can be returned for bid >= 2. Done File src/mainboard/google/guybrush/variants/nipperkin/gpio.c: https://review.coreboot.org/c/coreboot/+/59053/comment/4b1e6da7_32435be7 PS2, Line 51: PAD_NC(GPIO_69), > this needs to be removed since nipperkin board version 2 uses GPIO69 as SD AUX RESET too, thanks. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:47:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Karthik Ramasubramanian. Hello build bot (Jenkins), Kevin Chiu, Raul Rangel, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59053 to look at the new patch set (#3). Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default and only overriding to GPIO_70 for guybrush bid==1. BUG=b:202992077 BRANCH=None TEST=Build and boot guybrush, SD card works Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/helpers.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/guybrush/variant.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/variant.c 6 files changed, 19 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59053/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Raul Rangel, Andrey Pronin, Kangheui Won, Julius Werner, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 ) Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... Patch Set 8: (6 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/58870/comment/b8886e3b_97943f58 PS5, Line 645: config RESUME_PATH_SAME_AS_BOOT > I'm checking CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME and it depends on RESUME_PATH_SAME_AS_BOO […] Done File src/mainboard/google/guybrush/Kconfig: https://review.coreboot.org/c/coreboot/+/58870/comment/5f36d7c0_993f0702 PS5, Line 12: select CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME > Not if HAVE_ACPI_RESUME is false. […] Done File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/58870/comment/5c430623_00b5610f PS7, Line 381: PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), > Good catch. The GPIO for GSC_SOC_INT_L moved from GPIO_3 to GPIO_85 in the latest schematic. […] Done File src/soc/amd/common/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/58870/comment/7d938ba0_d05bdc73 PS5, Line 230: verstage_mainboard_s0i3_init(); > Yes it can hurt. […] Done File src/soc/amd/common/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/58870/comment/c1f016e4_d8e78602 PS6, Line 284: unmap_fch_devices(); > Nit: Can be moved inside psp_verstage_s0i3_resume(). Done File src/vendorcode/google/chromeos/Kconfig: https://review.coreboot.org/c/coreboot/+/58870/comment/73d97577_97f57572 PS3, Line 47: depends on TPM2 && RESUME_PATH_SAME_AS_BOOT > OK. Let's not depend on RESUME_PATH_SAME_AS_BOOT for this CL. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 8 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:33:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Rob Barnes <robbarnes(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add variant_tpm_gpio_table
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59083 ) Change subject: mb/google/guybrush: Add variant_tpm_gpio_table ...................................................................... mb/google/guybrush: Add variant_tpm_gpio_table Add separate gpio table for TPM i2c and interrupt. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/guybrush/verstage.c M src/security/vboot/vboot_common.h 6 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59083/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 7bd392f..3b6ee6e 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -251,6 +251,15 @@ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), }; +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + /* Power-on timing requirements: * Fibocom 350-GL: * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min @@ -397,6 +406,12 @@ return espi_gpio_table; } +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + __weak void variant_fpmcu_reset(void) { size_t size; diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 0ebc59a..e94a596 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -49,6 +49,9 @@ /* This function provides GPIO settings for eSPI bus. */ const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + /* Finalize GPIOs, such as FPMCU power */ void variant_finalize_gpios(void); diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 4634c5a..0f8bc04 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -81,6 +81,15 @@ PAD_NC(GPIO_32), }; +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -130,3 +139,9 @@ *size = ARRAY_SIZE(fpmcu_disable_gpio_table); return fpmcu_disable_gpio_table; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 6a12ad3..c8d4d1e 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -92,6 +92,26 @@ PAD_NC(GPIO_3), }; +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -149,3 +169,16 @@ *size = ARRAY_SIZE(bid2_fpmcu_disable_gpio_table); return bid2_fpmcu_disable_gpio_table; } + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_tpm_gpio_table); + return bid1_tpm_gpio_table; + } + + *size = ARRAY_SIZE(bid2_tpm_gpio_table); + return bid2_tpm_gpio_table; +} diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index 163caeb..95762254 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -65,3 +65,15 @@ setup_espi_mux(); } + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index d7b549c..0e5fb826 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -44,6 +44,7 @@ void verstage_main(void); void verstage_mainboard_early_init(void); void verstage_mainboard_espi_init(void); +void verstage_mainboard_tpm_init(void); void verstage_mainboard_init(void); /* Check boot modes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Gerrit-Change-Number: 59083 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Add variant_espi_gpio_table
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Julius Werner, Yu-Ping Wu. Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59082 ) Change subject: mb/google/guybrush: Add variant_espi_gpio_table ...................................................................... mb/google/guybrush: Add variant_espi_gpio_table Add separate gpio table for eSPI bus. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/verstage.c M src/security/vboot/vboot_common.h 4 files changed, 65 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59082/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 66b40be..7bd392f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -234,6 +234,23 @@ PAD_GPI(GPIO_91, PULL_NONE), }; +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), +}; + /* Power-on timing requirements: * Fibocom 350-GL: * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min @@ -374,6 +391,12 @@ return fpmcu_disable_gpio_table; } +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + __weak void variant_fpmcu_reset(void) { size_t size; diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 6cc96f8..0ebc59a 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -46,6 +46,9 @@ /* This function provides GPIO settings for fpmcu disable. */ const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + /* Finalize GPIOs, such as FPMCU power */ void variant_finalize_gpios(void); diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index e6434df..163caeb 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -21,24 +21,47 @@ } } + +/* +* TODO : Make common function in cezanne code and just call it +* when PCI access is fixed in the PSP (b/186602472). +* For now the PSP doesn't configure LPC so it should be fine. +*/ +static void setup_espi_mux(void) +{ + uint32_t dword; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + printk(BIOS_DEBUG, "Verstage configure eSPI\n"); + + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword); + + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); +} + void verstage_mainboard_early_init(void) { setup_gpio(); - /* - * TODO : Make common function in cezanne code and just call it - * when PCI access is fixed in the PSP (b/186602472). - * For now the PSP doesn't configure LPC so it should be fine. - */ - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - uint32_t dword; - printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_io_write32(PM_SPI_PAD_PU_PD, dword); + setup_espi_mux(); +} - dword = pm_io_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_io_write32(PM_ACPI_CONF, dword); - } +void verstage_mainboard_espi_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); + + setup_espi_mux(); } diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 512da0e..d7b549c 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -43,6 +43,7 @@ */ void verstage_main(void); void verstage_mainboard_early_init(void); +void verstage_mainboard_espi_init(void); void verstage_mainboard_init(void); /* Check boot modes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Gerrit-Change-Number: 59082 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Raul Rangel, Andrey Pronin, Kangheui Won, Julius Werner, Karthik Ramasubramanian. Hello build bot (Jenkins), Jason Glenesk, Andrey Pronin, Raul Rangel, Marshall Dawson, Kangheui Won, Julius Werner, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58870 to look at the new patch set (#8). Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... soc/amd/psp_verstage: Init TPM on S0i3 resume Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. eSPI is initialized so board_id can be accessed. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. 50-100ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/Kconfig M src/security/vboot/vboot_common.h M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 5 files changed, 75 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/58870/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 8 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/psp_verstage: Get vb2_context early
by Rob Barnes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59017 to look at the new patch set (#2). Change subject: soc/amd/psp_verstage: Get vb2_context early ...................................................................... soc/amd/psp_verstage: Get vb2_context early Calling reboot_into_recovery with NULL context fails. Initialize ctx early so it can be used for reboot_into_recovery if an error occurs. BUG=None TEST=Boot guybrush, suspend/resume guybrush BRANCH=None Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/common/psp_verstage/psp_verstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/59017/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Gerrit-Change-Number: 59017 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Nick Vaccaro (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/58351/comment/50d77622_32d57d45 PS7, Line 333: exit if SoC does not export a list > this doesn't look true? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:26:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs
by EricR Lai (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tracy Wu, Kane Chen, Tim Wawrzynczak, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P PEG Device IDs ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/pcie/pcie.c: https://review.coreboot.org/c/coreboot/+/59081/comment/c7b1d763_dfe5e02d PS1, Line 316: PCIE > Hi Eric, […] hmm, Can we make this more clear for other people? :p I don't understand this unless you explain to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 1 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 04:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021