coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/guybrush/dewatt: update dewatt config
by Chris Wang (Code Review) 10 Nov '21

10 Nov '21

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59092 ) Change subject: mb/google/guybrush/dewatt: update dewatt config ...................................................................... mb/google/guybrush/dewatt: update dewatt config copy config from guybrush reference board. BUG=b:204151079 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59092/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index c182265..5a0ad98 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -4,4 +4,54 @@ device domain 0 on end # domain + + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "15000" + register "thermctl_limit_degreeC" = "100" + + #Update values based on final stardust SDLE test report. + register "telemetry_vddcrvddfull_scale_current_mA" = "94648" #mA + register "telemetry_vddcrvddoffset" = "785" + register "telemetry_vddcrsocfull_scale_current_mA" = "30314" #mA + register "telemetry_vddcrsocoffset" = "560" + + # I2C Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Speaker, Codec, P-SAR | + #| I2C3 | H1/D2 TPM | + #+-------------------+---------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + device ref i2c_0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + end # I2C0 end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/59092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Gerrit-Change-Number: 59092 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 10 Nov '21

10 Nov '21

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Change in coreboot[master]: [WIP] util: Add coreboot Configurator
by Sean Rhodes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Sean Rhodes, Martin Roth, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58854 to look at the new patch set (#41). Change subject: [WIP] util: Add coreboot Configurator ...................................................................... [WIP] util: Add coreboot Configurator A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1 --- M 3rdparty/blobs A util/coreboot-configurator/README.md A util/coreboot-configurator/contrib/PKGBUILD A util/coreboot-configurator/contrib/README.md A util/coreboot-configurator/contrib/debian/changelog A util/coreboot-configurator/contrib/debian/compat A util/coreboot-configurator/contrib/debian/control A util/coreboot-configurator/contrib/debian/files A util/coreboot-configurator/contrib/debian/rules A util/coreboot-configurator/contrib/debian/source/format A util/coreboot-configurator/contrib/flatpak/coreboot-configurator.json A util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json A util/coreboot-configurator/meson.build A util/coreboot-configurator/meson_options.txt A util/coreboot-configurator/screenshots/coreboot-configurator.gif A util/coreboot-configurator/screenshots/coreboot-configurator.png A util/coreboot-configurator/src/application/aboutwindow.cpp A util/coreboot-configurator/src/application/aboutwindow.h A util/coreboot-configurator/src/application/aboutwindow.ui A util/coreboot-configurator/src/application/categories.yaml A util/coreboot-configurator/src/application/configuration.cpp A util/coreboot-configurator/src/application/configuration.h A util/coreboot-configurator/src/application/corebootconfigurator.cpp A util/coreboot-configurator/src/application/corebootconfigurator.h A util/coreboot-configurator/src/application/corebootconfigurator.ui A util/coreboot-configurator/src/application/images.qrc A util/coreboot-configurator/src/application/main.cpp A util/coreboot-configurator/src/application/meson.build A util/coreboot-configurator/src/application/nvramtoolcli.cpp A util/coreboot-configurator/src/application/nvramtoolcli.h A util/coreboot-configurator/src/application/qtyaml.h A util/coreboot-configurator/src/application/toggle-off.svg A util/coreboot-configurator/src/application/toggle-on.svg A util/coreboot-configurator/src/application/toggleswitch.cpp A util/coreboot-configurator/src/application/toggleswitch.h A util/coreboot-configurator/src/application/util.h A util/coreboot-configurator/src/meson.build A util/coreboot-configurator/src/static/aboutIcon.png A util/coreboot-configurator/src/static/categories.yaml A util/coreboot-configurator/src/static/coreboot-configurator.desktop A util/coreboot-configurator/src/static/coreboot_configurator.svg A util/coreboot-configurator/src/static/meson.build A util/coreboot-configurator/src/static/org.coreboot.nvramtool.policy A util/coreboot-configurator/src/static/org.coreboot.reboot.policy 44 files changed, 3,159 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/58854/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/58854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie654f6aca57a792be0c295afc081a95ed4d875d1 Gerrit-Change-Number: 58854 Gerrit-PatchSet: 41 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kano: set power limits for thermal
by David Wu (Code Review) 10 Nov '21

10 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59091 ) Change subject: mb/google/brya/var/kano: set power limits for thermal ...................................................................... mb/google/brya/var/kano: set power limits for thermal Set power limits for kano based on CPU SKUs. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 --- M src/mainboard/google/brya/variants/kano/Makefile.inc A src/mainboard/google/brya/variants/kano/ramstage.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59091/1 diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc index 9ea19de..66dcf7e 100644 --- a/src/mainboard/google/brya/variants/kano/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -6,3 +6,4 @@ ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c new file mode 100644 index 0000000..4b8b4e5 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19 Gerrit-Change-Number: 59091 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. flora.fu(a)mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58969 ) Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... Patch Set 9: (3 comments) File src/soc/mediatek/mt8195/apusys_devapc.c: https://review.coreboot.org/c/coreboot/+/58969/comment/2984a48c_ef51b72b PS6, Line 196: ARRAY_SIZE(apusys_noc_dapc) > Then can we check the values are the same somewhere? […] OK! Add add checking under array declaration. File src/soc/mediatek/mt8195/apusys_devapc.c: https://review.coreboot.org/c/coreboot/+/58969/comment/c9b7d324_9c5d2fdd PS8, Line 237: > Also print i? Same below. Done File src/soc/mediatek/mt8195/apusys_devapc.c: https://review.coreboot.org/c/coreboot/+/58969/comment/a4ce67ba_5a9b214d PS9, Line 46: APUSYS_NOC_DAPC_AO_SLAVE_NUM add checking for compile time. -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 9 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 07:35:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add APU device apc driver
by flora.fu＠mediatek.com (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, flora.fu(a)mediatek.com. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58969 to look at the new patch set (#9). Change subject: soc/mediatek/mt8195: Add APU device apc driver ...................................................................... soc/mediatek/mt8195: Add APU device apc driver Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slaves are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, other domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/devapc.c M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/apusys_devapc.h 5 files changed, 330 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58969/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Gerrit-Change-Number: 58969 Gerrit-PatchSet: 9 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Refactor the SMBIOS type 17 write function
by Jakub Czapiga (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Subrata Banik, Angel Pons, Rob Barnes, Patrick Rudolph, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56628 ) Change subject: arch/x86: Refactor the SMBIOS type 17 write function ...................................................................... Patch Set 24: (3 comments) File src/include/spd.h: https://review.coreboot.org/c/coreboot/+/56628/comment/5a6f3a6b_337bee6e PS24, Line 201: SPD_UNDEFINED 0x00 I think, this should stay. Using DDR2_SPD_UNDEFINED, DDR3_SPD_UNDEFINED etc is weird to me. File tests/lib/dimm_info_util-test.c: https://review.coreboot.org/c/coreboot/+/56628/comment/d0309f78_2ac946d0 PS24, Line 109: DDR2_SPD_UNDEFINED Why not the DDR3_SPD_UNDEFINED or LPX_SPD_UNDEFINED? I think, that SPD_UNDEFINED should stay in src/include/spd.h, and also here https://review.coreboot.org/c/coreboot/+/56628/comment/154c6f21_e39aecdb PS24, Line 151: MEMORY_TYPE_DDR2, { DDR2_SPD_UDIMM, DDR2_SPD_MICRO_DIMM, : DDR2_SPD_MINI_UDIMM }, { DDR2_SPD_RDIMM, DDR2_SPD_MINI_RDIMM }, : DDR2_SPD_SODIMM Please, use named fields. It will increase readability :) -- To view, visit https://review.coreboot.org/c/coreboot/+/56628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Gerrit-Change-Number: 56628 Gerrit-PatchSet: 24 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 07:21:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add _DSM method for CNVi WiFi
by Ronak Kanabar (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Saurabh Mishra, Maulik V Vaghela, Tim Wawrzynczak, Sumeet R Pawnikar, Ravindra, Subrata Banik, Balaji Manigandan, Patrick Rudolph. Hello build bot (Jenkins), Saurabh Mishra, Maulik V Vaghela, Tim Wawrzynczak, Sumeet R Pawnikar, Ravindra, Subrata Banik, Balaji Manigandan, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58324 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Add _DSM method for CNVi WiFi ...................................................................... soc/intel/alderlake: Add _DSM method for CNVi WiFi Coreboot need to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This patch adds _DSM method for that. Add support for following 2 function in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable BUG=b:201724512 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: Iebb234d4e2e3f60d65fa76d41db4c7eea6324437 --- M src/soc/intel/alderlake/acpi.c A src/soc/intel/alderlake/acpi/cnvi_wifi.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/alderlake/chip.c 4 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58324/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb234d4e2e3f60d65fa76d41db4c7eea6324437 Gerrit-Change-Number: 58324 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/common/block: Add CRFI field into globalnvs
by Ronak Kanabar (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Saurabh Mishra, Maulik V Vaghela, Ravindra, Sumeet R Pawnikar, Subrata Banik, Balaji Manigandan, Patrick Rudolph. Hello Saurabh Mishra, Maulik V Vaghela, Ravindra, Sumeet R Pawnikar, Subrata Banik, Balaji Manigandan, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58323 to look at the new patch set (#6). Change subject: intel/common/block: Add CRFI field into globalnvs ...................................................................... intel/common/block: Add CRFI field into globalnvs Add the CRFI fields to the GNVS. coreboot needs to propagate the value of CnviDdrRfim to the CNVi driver via the Wi-Fi DSM ACPI object. Wi-Fi driver consumes the value part of the Wi-Fi driver initialize. BUG=b:201724512 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: I0c64ae7a220c1551f2c61ab92c0ca0ec8b235745 --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/58323/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c64ae7a220c1551f2c61ab92c0ca0ec8b235745 Gerrit-Change-Number: 58323 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration
by Ronak Kanabar (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Srinidhi N Kaushik, Patrick Rudolph. Hello Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58132 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration ...................................................................... soc/intel/alderlake: Add the CnviDdrRfimDisable configuration FSP v2374_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfimDisable config to control the CnviDdrRfim UPD from devicetree. Setting CnviDdrRfimDisable to 1 disables CNVi DDR RFIM BUG=b:201724512 BRANCH=None TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value. Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/58132/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Gerrit-Change-Number: 58132 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021