coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/kano: Add thermal sensor settings
by David Wu (Code Review) 10 Nov '21

10 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59089 ) Change subject: mb/google/brya/var/kano: Add thermal sensor settings ...................................................................... mb/google/brya/var/kano: Add thermal sensor settings Kano has 3 thermal sensors, so add the missing sensor settings. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59089/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 899dd36..7ac6b81 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -40,7 +40,8 @@ chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""FAN"" + register "options.tsr[2].desc" = ""Charger"" # TODO: below values are initial reference values only ## Active Policy @@ -60,6 +61,7 @@ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), }" ## Critical Policy @@ -67,6 +69,7 @@ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), }" register "controls.power_limits" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/59089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Gerrit-Change-Number: 59089 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brask: Make LAN driver to support RT8125
by Alan Huang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Zhuohao Lee. Hello David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59086 to look at the new patch set (#2). Change subject: mb/google/brya/var/brask: Make LAN driver to support RT8125 ...................................................................... mb/google/brya/var/brask: Make LAN driver to support RT8125 Add new device id 0x8125 to the driver. BUG=b:193750191 BRANCH=None TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 2 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/brask: Configurate the GPIOs of LAN
by Alan Huang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58105 ) Change subject: mb/google/brya/var/brask: Configurate the GPIOs of LAN ...................................................................... Patch Set 6: (5 comments) File src/drivers/net/r8168.c: PS5: > Changes in this file should be split into a separate change that comes before the mainboard changes […] Separate to https://review.coreboot.org/c/coreboot/+/59086 File src/mainboard/google/brya/variants/brask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58105/comment/d3a71ee9_4824265a PS5, Line 84: 0x05af > This is incorrect. Let's define the led in the buganizer. Separate to https://review.coreboot.org/c/coreboot/+/59088 https://review.coreboot.org/c/coreboot/+/58105/comment/9344a65d_aa8aa042 PS5, Line 85: register "wake" = "0" > I think you can remove this but let's follow up b/204289108 to see if we need to change the wakeup p […] Done https://review.coreboot.org/c/coreboot/+/58105/comment/c2e6b87c_f751d0f1 PS5, Line 86: register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" > IIUC, this setting will disable the wake on lan. […] From 8125 spec., this pin will not disable wake-on-lan. We will double check it. https://review.coreboot.org/c/coreboot/+/58105/comment/a250fef6_4c4c8878 PS5, Line 90: register "device_index" = "0" > not required, the default value is already `0` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 6 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 10 Nov 2021 06:25:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brask: Customize the LED of RT8125
by Alan Huang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tim Wawrzynczak. Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59088 ) Change subject: mb/google/brya/var/brask: Customize the LED of RT8125 ...................................................................... mb/google/brya/var/brask: Customize the LED of RT8125 Add Kconfig item RT8168_SET_LED_MODE to enable LED customization. Update the LED settings in devicetree. BUG=b:193750191 BRANCH=None TEST=Build Pass Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: I6565f19b0ca7611c4731c4ae6365f17fbe63a7e9 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/59088/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index accba51..d138389 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -8,6 +8,7 @@ def_bool n select SPD_CACHE_IN_FMAP select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index d54a498..8bc56eb 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -81,6 +81,7 @@ end device ref pcie_rp7 on chip drivers/net + register "customized_leds" = "0x05af" device pci 00.0 on end end end # RTL8125 Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/59088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6565f19b0ca7611c4731c4ae6365f17fbe63a7e9 Gerrit-Change-Number: 59088 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brask: Enable LAN driver to write MAC
by Alan Huang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tim Wawrzynczak. Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59087 ) Change subject: mb/google/brya/var/brask: Enable LAN driver to write MAC ...................................................................... mb/google/brya/var/brask: Enable LAN driver to write MAC Turn on the LAN device in devicetree and add Kconfig item RT8168_GET_MAC_FROM_VPD to support writting MAC address. BUG=b:193750191 BRANCH=None TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD. Use 'ifconfig' to check if the MAC written successfully. Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59087/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e6e44e2..accba51 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n select SPD_CACHE_IN_FMAP + select RT8168_GET_MAC_FROM_VPD if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 3805666..d54a498 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -79,6 +79,11 @@ device generic 0 alias dptf_policy on end end end + device ref pcie_rp7 on + chip drivers/net + device pci 00.0 on end + end + end # RTL8125 Ethernet NIC device ref pcie4_0 on # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/59087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Gerrit-Change-Number: 59087 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brask: Make LAN driver to support RT8125
by Alan Huang (Code Review) 10 Nov '21

10 Nov '21

Alan Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: mb/google/brya/var/brask: Make LAN driver to support RT8125 ...................................................................... mb/google/brya/var/brask: Make LAN driver to support RT8125 Add new device id 0x8125 to the driver. BUG=b:193750191 BRANCH=None TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 --- M src/drivers/net/r8168.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/1 diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 18e2aff..87fc151 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -360,10 +360,16 @@ #endif }; +static const unsigned short pci_device_ids[] = { + 0x8186, + 0x8125, + 0 +}; + static const struct pci_driver r8168_driver __pci_driver = { .ops = &r8168_ops, .vendor = 0x10ec, - .device = 0x8168, + .devices = pci_device_ids, }; struct chip_operations drivers_net_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brask: Configurate the GPIOs of LAN
by Alan Huang (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: David Wu, Alan Huang. Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58105 to look at the new patch set (#6). Change subject: mb/google/brya/var/brask: Configurate the GPIOs of LAN ...................................................................... mb/google/brya/var/brask: Configurate the GPIOs of LAN Copy the default configuration from Puff. Update the 'stop_gpio' to GPP_H22. Remove 'wake'. ("WAKE#" is not a GPIO pin.) BUG=b:193750191 BRANCH=None TEST=Build Pass Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/58105/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Gerrit-Change-Number: 58105 Gerrit-PatchSet: 6 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs
by Tracy Wu (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tracy Wu, Kane Chen, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Kane Chen, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59081 to look at the new patch set (#2). Change subject: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs ...................................................................... soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs List of changes: 1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h 2. Add these new IDs into pcie_device_ids[] in pcie.c BUG=b:205668996 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/59081/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 2 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kano: Configure USB2 and USB3 port
by David Wu (Code Review) 10 Nov '21

10 Nov '21

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59084 ) Change subject: mb/google/brya/var/kano: Configure USB2 and USB3 port ...................................................................... mb/google/brya/var/kano: Configure USB2 and USB3 port 1. Disable unused USB2 and USB3 port 2. Enable MLB USB Type-A Port BUG=b:192370253 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59084/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index f2b04db..e82462d 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -18,6 +18,14 @@ # GPE configuration register "pmc_gpe0_dw1" = "GPP_D" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable M.2 Bluetooth + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/59084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 Gerrit-Change-Number: 59084 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE
by Werner Zeh (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph, Nico Huber, Martin Roth, Mario Scheithauer, Lean Sheng Tan, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 ) Change subject: soc/intel/elkhartlake: Introduce Intel PSE ...................................................................... Patch Set 52: (1 comment) File src/soc/intel/elkhartlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55367/comment/c95516a7_aad97514 PS2, Line 58: pse.bin-align := 0x1000 > I agree with Angel here. […] Yes, all the arguments are valid and the alignment has been removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/55367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea08fb82fea18ef66bab04b3ce378e79a0afbf7 Gerrit-Change-Number: 55367 Gerrit-PatchSet: 52 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 05:16:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021