Attention is currently required from: Arthur Heymans, Martin Roth, ron minnich, Stefan Reinauer, Angel Pons, Keith Hui, Patrick Rudolph, Felix Held.
Arthur Heymans has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55068 )
Change subject: [WIP]Allow to build romstage sources inside the bootblock
......................................................................
[WIP]Allow to build romstage sources inside the bootblock
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
TODO make this option only visible when it makes sense
TESTED: works on qemu x86, arm and aarch64.
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/Kconfig
M src/arch/arm64/romstage.c
M src/arch/x86/Makefile.inc
M src/include/memlayout.h
M src/include/rules.h
M src/lib/cbfs.c
M src/lib/prog_loaders.c
M src/mainboard/emulation/qemu-armv7/romstage.c
9 files changed, 42 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/7
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55070 )
Change subject: [NOTFORMERGE]link Agesa into bootblock
......................................................................
Patch Set 5:
(1 comment)
File src/drivers/amd/agesa/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132926):
https://review.coreboot.org/c/coreboot/+/55070/comment/d4b3fb17_2cfd49f8
PS5, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
function definition argument 'void' should also have an identifier name
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Attention is currently required from: Arthur Heymans, Martin Roth, ron minnich, Stefan Reinauer, Angel Pons, Keith Hui, Patrick Rudolph, Felix Held.
Arthur Heymans has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55068 )
Change subject: [WIP]Allow to build romstage sources inside the bootblock
......................................................................
[WIP]Allow to build romstage sources inside the bootblock
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
For now this feature is x86 only, but it would be easy to change that
for other arch.
TODO make this option only visible when it makes sense
TESTED: works on qemu x86
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/Kconfig
M src/arch/arm64/romstage.c
M src/arch/x86/Makefile.inc
M src/include/memlayout.h
M src/include/rules.h
M src/lib/cbfs.c
M src/lib/prog_loaders.c
M src/mainboard/emulation/qemu-armv7/romstage.c
9 files changed, 42 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/6
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Change subject: arch/x86: Add a common romstage entry
......................................................................
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.inc
A src/arch/x86/romstage.c
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/romstage.c
A src/include/romstage_common.h
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/example/min86/romstage.c
9 files changed, 38 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55067/5
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59017 )
Change subject: soc/amd/psp_verstage: Get vb2_context early
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/59017/comment/d9cb08cd_16026fc5
PS1, Line 224:
> Yeah, since this is super early in RO code, I don't think there is anything we can do... […]
Whatever we choose between `svc_exit`, `die` or `assert` I'm okay with it if it's not a `reboot_into_recovery`.
Filed b/205894188 for svc_write_postcode.
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Change subject: [NOTFORMERGE]link Agesa into bootblock
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/amd/agesa/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132923):
https://review.coreboot.org/c/coreboot/+/55070/comment/bf409c23_8d7e0979
PS4, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
function definition argument 'void' should also have an identifier name
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Arthur Heymans has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55067 )
Change subject: arch/x86: Add a common romstage entry
......................................................................
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.inc
A src/arch/x86/romstage.c
M src/cpu/intel/car/romstage.c
M src/drivers/amd/agesa/romstage.c
A src/include/romstage_common.h
M src/soc/amd/cezanne/romstage.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/example/min86/romstage.c
9 files changed, 38 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/55067/4
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Change subject: drivers/intel/agesa/romstage.c: Move timestamp and console init up
......................................................................
drivers/intel/agesa/romstage.c: Move timestamp and console init up
Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/romstage.c
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/55066/3
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Change subject: drivers/amd/agesa/romstage.c: Remove lapic_id check
......................................................................
drivers/amd/agesa/romstage.c: Remove lapic_id check
The APs don't execute this codepath but ap_romstage_main().
Change-Id: If884001bc8c5363efbbf00422a9a700896318f7b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/romstage.c
1 file changed, 4 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55065/3
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59070 )
Change subject: soc/amd/cezanne/fsp_m_parameters: add curly braces around else block
......................................................................
soc/amd/cezanne/fsp_m_parameters: add curly braces around else block
Since the if block contains multiple statements, it uses curly braces
around them, so also add curly braces around the else block even though
it only contains one statement.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59070
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/cezanne/fsp_m_params.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 048b428..51e04e1 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -153,9 +153,9 @@
mcfg->usb_phy->Version_Major = 0xd;
mcfg->usb_phy->Version_Minor = 0x6;
mcfg->usb_phy->TableLength = 100;
- }
- else
+ } else {
mcfg->usb_phy = NULL;
+ }
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475
Gerrit-Change-Number: 59070
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged