coreboot-gerrit November 2021

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Change in coreboot[master]: device/pci_device.c: Improve pci_bridge_route() readability
by Arthur Heymans (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59131 to review the following change. Change subject: device/pci_device.c: Improve pci_bridge_route() readability ...................................................................... device/pci_device.c: Improve pci_bridge_route() readability Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Using an union/struct removes the need to juggle with bitwise operations. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/pci_device.c 1 file changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59131/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4b5e73b..a86605e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1333,7 +1333,15 @@ { struct device *dev = link->dev; struct bus *parent = dev->bus; - u32 reg, buses = 0; + union { + u32 raw; + struct { + u8 primary; + u8 secondary; + u8 subordinate; + u8 _latency; + } __packed; + } reg, buses = { .raw = 0 }; if (state == PCI_ROUTE_SCAN) { link->secondary = parent->subordinate + 1; @@ -1341,15 +1349,16 @@ } if (state == PCI_ROUTE_CLOSE) { - buses |= 0xfeff << 8; + buses.primary = 0xff; + buses.secondary = 0xfe; } else if (state == PCI_ROUTE_SCAN) { - buses |= parent->secondary & 0xff; - buses |= ((u32) link->secondary & 0xff) << 8; - buses |= 0xff << 16; /* MAX PCI_BUS number here */ + buses.primary = parent->secondary; + buses.secondary = parent->secondary; + buses.subordinate = 0xff; /* MAX PCI_BUS number here */ } else if (state == PCI_ROUTE_FINAL) { - buses |= parent->secondary & 0xff; - buses |= ((u32) link->secondary & 0xff) << 8; - buses |= ((u32) link->subordinate & 0xff) << 16; + buses.primary = parent->secondary; + buses.secondary = parent->secondary; + buses.subordinate = link->subordinate; } if (state == PCI_ROUTE_SCAN) { @@ -1364,11 +1373,11 @@ * transactions will not be propagated by the bridge if it is not * correctly configured. */ - - reg = pci_read_config32(dev, PCI_PRIMARY_BUS); - reg &= 0xff000000; - reg |= buses; - pci_write_config32(dev, PCI_PRIMARY_BUS, reg); + reg.raw = pci_read_config32(dev, PCI_PRIMARY_BUS); + reg.primary = buses.primary; + reg.secondary = buses.secondary; + reg.subordinate = buses.subordinate; + pci_write_config32(dev, PCI_PRIMARY_BUS, reg.raw); if (state == PCI_ROUTE_FINAL) { pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); -- To view, visit https://review.coreboot.org/c/coreboot/+/59131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Gerrit-Change-Number: 59131 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/thread: Start stopwatch after printk
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58960 ) Change subject: lib/thread: Start stopwatch after printk ...................................................................... lib/thread: Start stopwatch after printk We are currently counting how long it takes to print the waiting message, in addition to the actual time we spent waiting. This results in inflating the measurement by 1.7ms when the serial console is enabled. This CL makes it so the print happens before the stopwatch starts. BUG=b:179699789 TEST=No longer see printk time taken into account on serial console Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58960 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/lib/thread.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, approved diff --git a/src/lib/thread.c b/src/lib/thread.c index 7d5cdc5..0393ca7 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -398,10 +398,10 @@ if (handle->state == THREAD_UNINITIALIZED) return CB_ERR_ARG; - stopwatch_init(&sw); - printk(BIOS_SPEW, "waiting for thread\n"); + stopwatch_init(&sw); + while (handle->state != THREAD_DONE) assert(thread_yield() == 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/58960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26 Gerrit-Change-Number: 58960 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59026 ) Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: lol, lost +2 on this one because I removed a line in the commit message... -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 21:15:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59130 ) Change subject: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I split this one out from CB:58988 so I can unblock parts of the patch train. -- To view, visit https://review.coreboot.org/c/coreboot/+/59130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Gerrit-Change-Number: 59130 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Nov 2021 21:14:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59130 ) Change subject: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA ...................................................................... soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA This will enable reading FSP-S/M using the SPI DMA controller. BUG=B:179699789 TEST=Build guybrush with SPI DMA enabled and verify alignment is set Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 --- M src/soc/amd/common/block/lpc/Kconfig 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/59130/1 diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index 76f4ec7..6419269 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,12 +16,20 @@ help Select this option to enable SPI DMA support. -# The LPC SPI DMA controller requires the destination buffers to be 64 byte +# The LPC SPI DMA controller requires the source and destination to be 64 byte # aligned. config CBFS_CACHE_ALIGN int default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA +config FSP_ALIGNMENT_FSP_S + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + +config FSP_ALIGNMENT_FSP_M + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/59130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Gerrit-Change-Number: 59130 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Raul Rangel (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59026 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... soc/amd/cezanne: Use LZ4 for FSP-S This change increases the fsps.bin by 20 KiB, but it decreases decompression time. When not using preloading we save about 4 ms, when using preloading we save about 6. BUG=b:179699789 TEST=Boot nipperkin to OS fsps.bin 0x4afc0 fsp 66253 LZMA (200704 decompressed) fsps.bin 0x45fc0 fsp 87157 LZ4 (200704 decompressed) - FSP-S / no async - | 505 - starting to verify keyblock/preamble (RSA) | 9.36 | 11.012 Δ( 1.65, 0.11%) | ... | 971 - loading FSP-S | 7.095 | 6.141 Δ( -0.95, -0.07%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.008 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 15.149 | 8.98 Δ( -6.17, -0.42%) | | 954 - calling FspSiliconInit | 0.038 | 0.037 Δ( -0.00, -0.00%) | - FSP-S / async - | 508 - finished loading body | 177.978 | 179.689 Δ( 1.71, 0.12%) | ... | 971 - loading FSP-S | 6.928 | 7.225 Δ( 0.30, 0.02%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.011 | 0.01 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 8.312 | 0.241 Δ( -8.07, -0.58%) | | 954 - calling FspSiliconInit | 0.091 | 0.09 Δ( -0.00, -0.00%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/59026/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Sean Rhodes (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Tim Crawford, Jeremy Soller, Tim Wawrzynczak, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 12: (1 comment) This change is ready for review. File src/soc/intel/tigerlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/58798/comment/a0977e39_9ba49d88 PS10, Line 190: Local0 |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING | : INTER_DOMAIN_USB4_INTERNET_PROTOCOL > Actually, does it make more sense to do something like this? […] Up to you, Google has more TGL boards than us and System76 combined but... isn't it the OS supporting SCM rather than TBT? (Windows 10 and Linux don't work) -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 21:02:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Tim Wawrzynczak (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Felix Singer, Sean Rhodes, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 12: Code-Review+2 (2 comments) Patchset: PS12: Feels like there has to be something more elegant, but I can't think of anything ATM, so let's go with this. File src/soc/intel/tigerlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/58798/comment/05f64570_2f03a044 PS12, Line 159: * nit: line up with the other `*` -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 19:48:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
by Tim Crawford (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Felix Singer, Sean Rhodes, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58798 ) Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Gerrit-Change-Number: 58798 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 19:44:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable CPU PCIE RP 1
by Tim Wawrzynczak (Code Review) 10 Nov '21

10 Nov '21

Attention is currently required from: Joey Peng, YH Lin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59080 ) Change subject: mb/google/brya/var/taeko: Enable CPU PCIE RP 1 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Gerrit-Change-Number: 59080 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Nov 2021 19:33:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021