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I'd like you to reexamine a change. Please visit
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Change subject: drivers/net/r8168: Add support for Realtek RT8125
......................................................................
drivers/net/r8168: Add support for Realtek RT8125
The Realtek RT8168 and RT8125 have a similar programming
interface, therefore add the PCI device ID for the RT8125
into driver for support.
BUG=b:193750191
BRANCH=None
TEST=emerge-brask coreboot chromeos-bootimage
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71
---
M src/drivers/net/r8168.c
M src/include/device/pci_ids.h
2 files changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/4
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Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 )
Change subject: drivers/net/r8168: Add support for Realtek RT8125
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59086/comment/0e8a9c1b_7e66b4fb
PS2, Line 7: mb/google/brya/var/brask: Make LAN driver to support RT8125
> suggestion: […]
Ack
https://review.coreboot.org/c/coreboot/+/59086/comment/f3ab000d_8467e162
PS2, Line 8:
: Add new device id 0x8125 to the driver.
> suggestion: […]
Ack
File src/drivers/net/r8168.c:
https://review.coreboot.org/c/coreboot/+/59086/comment/3ca17c81_673ef669
PS2, Line 364: 0x8168,
: 0x8125,
> Now that there is more than one, should we add these to https://review.coreboot. […]
Ack
https://review.coreboot.org/c/coreboot/+/59086/comment/ed916890_99d6ce3e
PS2, Line 371: 0x10ec
> While you're here, do you mind changing this to `PCI_VENDOR_ID_REALTEK` ?
Ack
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Hello build bot (Jenkins), David Wu, Tim Wawrzynczak, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: drivers/net/r8168: Add support for Realtek RT8125
......................................................................
drivers/net/r8168: Add support for Realtek RT8125
The Realtek RT8168 and RT8125 have a similar programming
interface, therefore add the PCI device ID for the RT8125
into driver for support.
BUG=b:193750191
BRANCH=None
TEST=emerge-brask coreboot chromeos-bootimage
Signed-off-by: Alan Huang <alan-huang(a)quanta.corp-partner.google.com>
Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71
---
M src/drivers/net/r8168.c
M src/include/device/pci_ids.h
2 files changed, 10 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/59086/3
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Malik Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59135 )
Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/brya/variants/primus/variant.c:
https://review.coreboot.org/c/coreboot/+/59135/comment/8309fed0_64965b5e
PS3, Line 25: if (board_ver > 1)
: return;
> i think you can move this check to the line 15. […]
Done
https://review.coreboot.org/c/coreboot/+/59135/comment/58e0f4c6_83a06fbd
PS3, Line 33: uint32_t board_ver = board_id();
> I would suggest to put this line to the function devtree_update_emmc_rtd3()
There is another function that also uses board_ver, so it will keep, thanks。
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Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................
mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less
than 1, do not enable RTD3 driver.
BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed
Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com>
Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727
---
M src/mainboard/google/brya/variants/primus/Makefile.inc
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus/overridetree.cb
A src/mainboard/google/brya/variants/primus/variant.c
4 files changed, 42 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/59135/4
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Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, Alan Huang, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"
......................................................................
Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"
This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af.
Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic.
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388
---
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59149/2
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Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/brya/variants/primus/variant.c:
https://review.coreboot.org/c/coreboot/+/59135/comment/71f51dce_ebd745fa
PS3, Line 25: if (board_ver > 1)
: return;
i think you can move this check to the line 15. Return immediately if the board doesn't need this modification.
https://review.coreboot.org/c/coreboot/+/59135/comment/8f9bdade_d26c9f9a
PS3, Line 33: uint32_t board_ver = board_id();
I would suggest to put this line to the function devtree_update_emmc_rtd3()
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David Wu has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/58578 )
Change subject: mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting
......................................................................
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Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................
Patch Set 2:
(5 comments)
File src/mainboard/google/brya/variants/primus/variant.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132931):
https://review.coreboot.org/c/coreboot/+/59135/comment/32113b04_5e2b01ee
PS2, Line 21: if (child->chip_ops == &soc_intel_common_block_pcie_rtd3_ops)
suspect code indent for conditional statements (16, 16)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132931):
https://review.coreboot.org/c/coreboot/+/59135/comment/91890acc_eb2d65c3
PS2, Line 22: rtd3_dev = child;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132931):
https://review.coreboot.org/c/coreboot/+/59135/comment/349e41f5_19a641b5
PS2, Line 22: rtd3_dev = child;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132931):
https://review.coreboot.org/c/coreboot/+/59135/comment/ba759143_e6077428
PS2, Line 28: rtd3_dev->enabled = 0;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132931):
https://review.coreboot.org/c/coreboot/+/59135/comment/39b4669c_5eb02610
PS2, Line 34: devtree_update_emmc_rtd3(board_ver);
please, no spaces at the start of a line
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