coreboot-gerrit November 2021

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Change in coreboot[master]: ChromeOS: Replace with or add <types.h>
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58996 ) Change subject: ChromeOS: Replace with or add <types.h> ...................................................................... ChromeOS: Replace with or add <types.h> It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 64 files changed, 64 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index e5f3b5c..14f89d1 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index bb0ffeea..cb904a0 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 2274ff7..3132fd7d 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -2,6 +2,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index a33caca..c51af1a 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 58 diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index e0a13b8..bf7f9eb 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -5,6 +5,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index d9cbdb0..ba4bbf8 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 73fad72..a28f873 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 356e97b..2de55b0 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -8,6 +8,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <ec/quanta/ene_kb3940q/ec.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 14efdc3..f0c1446 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <gpio.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The WP status pin lives on MF_ISH_GPIO_4 */ diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 7599295..00fa126 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -5,6 +5,7 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <bootmode.h> diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 0d75ac3..e5ae163 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -5,6 +5,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 9b3bd70..864bb29 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index dbdb273..3d17a6c 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -8,6 +8,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> #include <device/device.h> diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index e3a9cd3..6122b85 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -6,6 +6,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> #include <device/device.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 73eae78..7c0cc96 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "gpio.h" diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index a9456e4..5ee822c 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -5,6 +5,7 @@ #include <gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index c448f05..71546aa 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index acd4cd6..1dff1ca 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index 6131322..3e54fa4 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -4,6 +4,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 354d839..3401b82 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -7,6 +7,7 @@ #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <variant/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a3cf60f..f9ffcd9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -3,7 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 5cfe9df..ff4cef6 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <ec/google/chromeec/ec.h> #include <soc/chromeos.h> diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index a386dd6..0a465c9 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <bootmode.h> #include <boot/coreboot_tables.h> diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 540803c..f4250cc 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index d0ceabc..9c260ab 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -5,6 +5,7 @@ #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index e599317..d16c4e1 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -3,7 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 03b0d47..77aa11a 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -9,6 +9,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <ec/compal/ene932/ec.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index ebbfdd3..07a13a3 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -6,6 +6,7 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index c9b91ad..ff39fbf 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -6,6 +6,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index d7be2c6..d3df99e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index f9a1718..773a807 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index a45ccdd..d258678 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -4,6 +4,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index fb32b3a..9bb3e45 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 807d161..de54929 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -3,7 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 3dc9f19..170013a 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -6,6 +6,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> #include <device/device.h> diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 4fffd45..5453583 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 07fdee3..e68093f 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -8,6 +8,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <ec/quanta/it8518/ec.h> diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 5f87821..20469d6 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -5,6 +5,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 164e9d2..ac8c5c2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index cfb55a7..35c002d 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <variant/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 85807a1..5fe89af 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -5,6 +5,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 3a8e629..8a04bd9 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 2b14014..b6c4164 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 1e02e3d..5c5003b 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -6,6 +6,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index b9d9429..9e5f243 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index e0f5faf..58732b1 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 7878a2a..dfdb66d 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -5,6 +5,7 @@ #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index eccfade..0b2c680 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 8a8bc42..6df26af 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -6,6 +6,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index e631a86..df06865 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index e631a86..df06865 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 320f92a..bf9a7bf 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -5,6 +5,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index e3ad962..82b3931 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index df01242..902cb19 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -6,6 +6,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "gpio.h" diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 3a99e25..09e9b7e 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -4,6 +4,7 @@ #include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "gpio.h" diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 052191f..e71314f 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -5,6 +5,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c index 2a7ce9c..f416e09 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index ad23ea1..3f80b68 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #define WP_GPIO GP_E_22 diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index cb9af47..4eeb679 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -5,6 +5,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 8bbd82a..f067af7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index c577eca..889d4e6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -2,7 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <commonlib/helpers.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Pad configuration in ramstage*/ diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 996eee2..5e01910 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> /* Compile-time settings for recovery mode. */ diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index aa96153..ea9c75d 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -7,6 +7,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 24 diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index c8fbf98..c15233c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 68 -- To view, visit https://review.coreboot.org/c/coreboot/+/58996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Gerrit-Change-Number: 58996 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: intel/strago: Fix some CHROMEOS guards
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58924 ) Change subject: intel/strago: Fix some CHROMEOS guards ...................................................................... intel/strago: Fix some CHROMEOS guards MAINBOARD_HAS_CHROMEOS always evaluates true for this board. The commentary about get_write_protect_state() was wrong, it's currently only called in ramstage. Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/chromeos.c 2 files changed, 7 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 21ae380..004a6a2 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -2,11 +2,11 @@ bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += ec.c +ramstage-y += gpio.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index c0ce968..ad23ea1 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -23,14 +23,13 @@ int get_write_protect_state(void) { /* - * The vboot loader queries this function in romstage. The GPIOs have + * This function might get queried early in romstage. The GPIOs have * not been set up yet as that configuration is done in ramstage. * Configuring this GPIO as input so that there isn't any ambiguity * in the reading. */ -#if ENV_ROMSTAGE - gpio_input_pullup(WP_GPIO); -#endif + if (ENV_ROMSTAGE_OR_BEFORE) + gpio_input_pullup(WP_GPIO); /* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO); 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/58924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Gerrit-Change-Number: 58924 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: [WIP,RFC] Clean up spinlocks
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Julius Werner, Karthikeyan Ramasubramanian, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59094 ) Change subject: [WIP,RFC] Clean up spinlocks ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59094/comment/79ac18a2_4be89f85 PS2, Line 14: IMO commit a98d302fe9 x86/smp/spinlock: Disable thread coop when taking spinlock : is wrong and should be reverted too. > I think there is a disconnect between spinlock and thread_mutex. > > spinlock was made to prevent more than 1 CPU from executing. As you said, yielding here is bad... > > thread_mutex was only meant to work with coop multi-threading to guard a resource. It is safe to yield while holding the mutex because a `thread_mutex_lock` will yield if it can't get the lock. > > So we have two options: > 1) Make a multi-cpu aware thread_mutex and replace all spin_locks. > 2) Disable thread_yield() while holding a spin lock. This can happen one of two ways: > 1) Provide thread_yield() some mechanism to determine if a spin lock is being held on the BSP. > 2) Have spin_lock just disable coop-multi-threading. > > Honestly, 2.2 is the easiest to grasp. If you want, I will rename `spin_lock` to `spin_lock_disable_coop` and `spin_unlock_enable_coop`. I am in favor of 1. This can also address the case with lack of udelay() from uart8250mem, since thread_mutex can be made a periodical yield. And I think 2.1 and 2.2 eat the DMA performance for romstage because there are few (none) calls to thread_yield() where console lock is not held. > > Now I am not going to -2 these threding and spinlock changes. Just understand your DMA performance currently relies on periodic context switches, and you really really should not rely on uart8250mem and printk() to satisfy that. > > Right. In my case the DMA controller can perform 64 KiB transactions. Large things like the payload require being armed twice. > > I'm not currently dependent on printk to satisfy that requirement. I'm adding more periodic yields to make it more predictable: https://review.coreboot.org/c/coreboot/+/58955 That improves the case for ramstage only. One might say it's really ugly hack to depend on console for the periodical yields() but the next alternative would be to scatter those yields() here and there. -- To view, visit https://review.coreboot.org/c/coreboot/+/59094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570 Gerrit-Change-Number: 59094 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:20:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: Add thermal sensor settings
by David Wu (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sumeet R Pawnikar, Peter Ou. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59089 ) Change subject: mb/google/brya/var/kano: Add thermal sensor settings ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/kano/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59089/comment/28e28af8_70b6f5c5 PS1, Line 63: CHARGER, TEMP_SENSOR_1 > Do you still want to throttle charger for sensor_1 which is mapped to FAN now as per your this code […] Done. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Gerrit-Change-Number: 59089 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Add a master header pointer as a regular cbfs file
by Patrick Georgi (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Arthur Heymans, Martin Roth. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59133 ) Change subject: Makefile.inc: Add a master header pointer as a regular cbfs file ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Who still needs the master header? It's legacy stuff. libpayload is just about to lose the need, so who else? -- To view, visit https://review.coreboot.org/c/coreboot/+/59133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99b8d4e2b4e9109b239804c86a1911ba916bd966 Gerrit-Change-Number: 59133 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs
by Tracy Wu (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Tracy Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59081 ) Change subject: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > couple questions: […] Yes, per FSP code and confirmed with our PCIe team, they are the same. -- To view, visit https://review.coreboot.org/c/coreboot/+/59081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Gerrit-Change-Number: 59081 Gerrit-PatchSet: 2 Gerrit-Owner: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 05:33:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: May I update the LED part in another commit? Verify the commit with correct LED settings? -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 5 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 05:06:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/net/r8168: Add support for Realtek RT8125
by Alan Huang (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: David Wu, Tim Wawrzynczak, Zhuohao Lee. Alan Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59086 ) Change subject: drivers/net/r8168: Add support for Realtek RT8125 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Gerrit-Change-Number: 59086 Gerrit-PatchSet: 5 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 05:03:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wifi/generic: fix package_size to align with WLAN driver
by Matt Chen (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sugnan Prabhu S, Paul Menzel, Kane Chen. Hello build bot (Jenkins), Sugnan Prabhu S, Kane Chen, Kane Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58951 to look at the new patch set (#6). Change subject: drivers/wifi/generic: fix package_size to align with WLAN driver ...................................................................... drivers/wifi/generic: fix package_size to align with WLAN driver Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3 no matter what the revision is for EWRD. It will pass the WLAN driver check then to retrieve the data properly. BUG=b:204414616 TEST= tested on brya with DRTU tool to verify if SAR table is read properly or not. Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Signed-off-by: Matt Chen <matt.chen(a)intel.corp-partner.google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/58951/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Gerrit-Change-Number: 58951 Gerrit-PatchSet: 6 Gerrit-Owner: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: Update CPPCv3 Nominal Frequency entry
by Sridhar Siricilla (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sugnan Prabhu S, Tim Wawrzynczak, Ravindra, Patrick Rudolph, Ravindra N. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57783 ) Change subject: cpu/intel/common: Update CPPCv3 Nominal Frequency entry ...................................................................... Patch Set 7: (2 comments) File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/57783/comment/97756513_55bf7fe5 PS4, Line 1799: printk(BIOS_DEBUG, "config->regs[0].addrl= %d, config->regs[0].addrh= %d\n", : config->regs[0].addrl, config->regs[0].addrh); > added for debug purpose Done File src/acpi/acpigen.c: https://review.coreboot.org/c/coreboot/+/57783/comment/efdca1e9_3eb8999e PS5, Line 1781: switch (config->version) { > > switch and case should be at the same indent […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If39e5e4ac77a71b143cdb5f043fb398abb398ee3 Gerrit-Change-Number: 57783 Gerrit-PatchSet: 7 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 04:41:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021