coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/cezanne: enable LPC decodes if platform uses LPC
by Karthik Ramasubramanian (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Jeremy Soller, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59103 ) Change subject: soc/amd/cezanne: enable LPC decodes if platform uses LPC ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/early_fch.c: https://review.coreboot.org/c/coreboot/+/59103/comment/ceb78ef7_565849f7 PS2, Line 50: if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) Should this be done here at this point? If so can you please capture the reason as a comment so that developers dont move it around accidentally. -- To view, visit https://review.coreboot.org/c/coreboot/+/59103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67 Gerrit-Change-Number: 59103 Gerrit-PatchSet: 2 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
by Zhuohao Lee (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Malik Hsu, Tim Wawrzynczak. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59135 ) Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Gerrit-Change-Number: 59135 Gerrit-PatchSet: 5 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:45:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Pack the PSP/BHD directory filling to functions
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59175 ) Change subject: amdfwtool: Pack the PSP/BHD directory filling to functions ...................................................................... Patch Set 1: (5 comments) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132949): https://review.coreboot.org/c/coreboot/+/59175/comment/9a50ea4a_2dbf0d05 PS1, Line 458: static void fill_psp_dirctory(embedded_firmware *amd_romsig, void *pspdir, 'dirctory' may be misspelled - perhaps 'directory'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132949): https://review.coreboot.org/c/coreboot/+/59175/comment/5b7ac936_54a79622 PS1, Line 469: static void fill_bios_dirctory(embedded_firmware *amd_romsig, void *biosdir, 'dirctory' may be misspelled - perhaps 'directory'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132949): https://review.coreboot.org/c/coreboot/+/59175/comment/b7a633dc_d85b3672 PS1, Line 1636: fill_psp_dirctory(amd_romsig, pspdir, &ctx, comboable, soc_id); 'dirctory' may be misspelled - perhaps 'directory'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132949): https://review.coreboot.org/c/coreboot/+/59175/comment/cec3970a_642dfbe2 PS1, Line 1640: fill_psp_dirctory(amd_romsig, combo_dir, &ctx, comboable, soc_id); 'dirctory' may be misspelled - perhaps 'directory'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132949): https://review.coreboot.org/c/coreboot/+/59175/comment/22b639f7_5ba78905 PS1, Line 1668: fill_bios_dirctory(amd_romsig, biosdir, &ctx, soc_id); 'dirctory' may be misspelled - perhaps 'directory'? -- To view, visit https://review.coreboot.org/c/coreboot/+/59175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2625c8858605c990da2225a16036b80ae31032f6 Gerrit-Change-Number: 59175 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 11 Nov 2021 06:45:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Pack the PSP/BHD directory filling to functions
by Bao Zheng (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59175 to review the following change. Change subject: amdfwtool: Pack the PSP/BHD directory filling to functions ...................................................................... amdfwtool: Pack the PSP/BHD directory filling to functions This two steps would be more complicated to handle more types of APU. Extract them to functions and then we can treat independently. More future cases can easily to be added. Change-Id: I2625c8858605c990da2225a16036b80ae31032f6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 45 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/59175/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 049755b..f054d7e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -455,6 +455,37 @@ } +static void fill_psp_dirctory(embedded_firmware *amd_romsig, void *pspdir, + context *ctx, uint8_t comboable, uint8_t soc_id) +{ + /* TODO: Change the flag comboable to specifi SOC ID. */ + (void) (&soc_id); + if (comboable) + amd_romsig->combo_psp_directory = BUFF_TO_RUN(*ctx, pspdir); + else + amd_romsig->psp_directory = BUFF_TO_RUN(*ctx, pspdir); +} + +static void fill_bios_dirctory(embedded_firmware *amd_romsig, void *biosdir, + context *ctx, uint8_t soc_id) +{ + switch (soc_id) { + case PLATFORM_RENOIR: + case PLATFORM_LUCIENNE: + case PLATFORM_CEZANNE: + amd_romsig->bios3_entry = BUFF_TO_RUN(*ctx, biosdir); + break; + case PLATFORM_MENDOCINO: + break; + case PLATFORM_STONEYRIDGE: + case PLATFORM_RAVEN: + case PLATFORM_PICASSO: + default: + amd_romsig->bios1_entry = BUFF_TO_RUN(*ctx, biosdir); + break; + } +} + static ssize_t copy_blob(void *dest, const char *src_file, size_t room) { int fd; @@ -490,17 +521,6 @@ return bytes; } -enum platform { - PLATFORM_UNKNOWN, - PLATFORM_STONEYRIDGE, - PLATFORM_RAVEN, - PLATFORM_PICASSO, - PLATFORM_RENOIR, - PLATFORM_CEZANNE, - PLATFORM_MENDOCINO, - PLATFORM_LUCIENNE, -}; - static uint32_t get_psp_id(enum platform soc_id) { uint32_t psp_id; @@ -1613,14 +1633,11 @@ amd_psp_fw_table, PSP_COOKIE, &cb_config); } - if (comboable) - amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, pspdir); - else - amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); + fill_psp_dirctory(amd_romsig, pspdir, &ctx, comboable, soc_id); #if PSP_COMBO psp_combo_directory *combo_dir = new_combo_dir(&ctx); - amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, combo_dir); + fill_psp_dirctory(amd_romsig, combo_dir, &ctx, comboable, soc_id); /* 0 -Compare PSP ID, 1 -Compare chip family ID */ combo_dir->entries[0].id_sel = 0; combo_dir->entries[0].id = get_psp_id(soc_id); @@ -1648,21 +1665,7 @@ integrate_bios_firmwares(&ctx, biosdir, NULL, amd_bios_table, BDT1_COOKIE, &cb_config); } - switch (soc_id) { - case PLATFORM_RENOIR: - case PLATFORM_LUCIENNE: - case PLATFORM_CEZANNE: - amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); - break; - case PLATFORM_MENDOCINO: - break; - case PLATFORM_STONEYRIDGE: - case PLATFORM_RAVEN: - case PLATFORM_PICASSO: - default: - amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); - break; - } + fill_bios_dirctory(amd_romsig, biosdir, &ctx, soc_id); } /* Free the filename. */ diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index a7ac7c1..d184f20 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -75,6 +75,17 @@ AMD_BIOS_SKIP } amd_bios_type; +enum platform { + PLATFORM_UNKNOWN, + PLATFORM_STONEYRIDGE, + PLATFORM_RAVEN, + PLATFORM_PICASSO, + PLATFORM_RENOIR, + PLATFORM_CEZANNE, + PLATFORM_MENDOCINO, + PLATFORM_LUCIENNE, +}; + struct second_gen_efs { /* todo: expand for Server products */ int gen:1; /* Client products only use bit 0 */ int reserved:31; -- To view, visit https://review.coreboot.org/c/coreboot/+/59175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2625c8858605c990da2225a16036b80ae31032f6 Gerrit-Change-Number: 59175 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/amd/agesa/romstage.c: Remove lapic_id check
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Arthur Heymans, Paul Menzel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55065 ) Change subject: drivers/amd/agesa/romstage.c: Remove lapic_id check ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If884001bc8c5363efbbf00422a9a700896318f7b Gerrit-Change-Number: 55065 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:41:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA
by Karthik Ramasubramanian (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Arthur Heymans, Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59130 ) Change subject: soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMA ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Gerrit-Change-Number: 59130 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:39:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Use LZ4 for FSP-S
by Karthik Ramasubramanian (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59026 ) Change subject: soc/amd/cezanne: Use LZ4 for FSP-S ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Gerrit-Change-Number: 59026 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:36:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
by Malik Hsu (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee. Malik Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59135 ) Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/brya/variants/primus/overridetree.cb: https://review.coreboot.org/c/coreboot/+/59135/comment/7b0e6d47_38dc5b6a PS4, Line 125: device generic 0 on end > suggestion: give this device a name, then see the comment below, this can be made a lot simpler now […] Done File src/mainboard/google/brya/variants/primus/variant.c: https://review.coreboot.org/c/coreboot/+/59135/comment/58e25fa1_f182ede7 PS4, Line 9: extern struct chip_operations soc_intel_common_block_pcie_rtd3_ops; : : static void devtree_update_emmc_rtd3(uint32_t board_ver) : { : struct device *rtd3_dev = NULL, *child = NULL; : struct device *pcie_rp3_dev = pcidev_path_on_root(PCH_DEVFN_PCIE3); : : if (board_ver > 1) : return; : : while ((child = dev_bus_each_child(pcie_rp3_dev->link_list, child)) != NULL) { : if (child->path.type != DEVICE_PATH_GENERIC) : continue; : if (child->path.generic.id != 0) : continue; : if (child->chip_ops == &soc_intel_common_block_pcie_rtd3_ops) : rtd3_dev = child; : } : rtd3_dev->enabled = 0; : } > This can be made simpler with the name given it from above: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Gerrit-Change-Number: 59135 Gerrit-PatchSet: 5 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 06:32:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
by Malik Hsu (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Malik Hsu, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59135 to look at the new patch set (#5). Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge ...................................................................... mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less than 1, do not enable RTD3 driver. BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 --- M src/mainboard/google/brya/variants/primus/Makefile.inc M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus/overridetree.cb A src/mainboard/google/brya/variants/primus/variant.c 4 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/59135/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Gerrit-Change-Number: 59135 Gerrit-PatchSet: 5 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: crossgcc: Upgrade toolchain
by HAOUAS Elyes (Code Review) 11 Nov '21

11 Nov '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59174 ) Change subject: crossgcc: Upgrade toolchain ...................................................................... crossgcc: Upgrade toolchain - Drop unused GCC_AUTOCONF_VERSION. - Clean-up Makefile: remove remaining lines uesd to build 'Make' - Upgrade acpica to 20210930 version - Upgrade CMake to 3.21.4 version - Upgrade llvm to 13.0.0 version Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/Makefile M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20210930_iasl.patch D util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20210930.tar.gz.cksum D util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-13.0.0.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-13.0.0.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.21.4.tar.gz.cksum D util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-13.0.0.src.tar.xz.cksum D util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-13.0.0.src.tar.xz.cksum 15 files changed, 10 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59174/1 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 288861b..cb552dd 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -27,9 +27,6 @@ bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) endif -build_make: - bash ./buildgcc -P make $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) - build_nasm: bash ./buildgcc -P nasm $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) @@ -68,7 +65,7 @@ distclean: clean rm -rf tarballs -.PHONY: all build_gcc build_iasl build_clang build_make build_nasm \ +.PHONY: all build_gcc build_iasl build_clang build_nasm \ clean distclean clean_tempfiles \ build-i386 build-x64 build-arm build-aarch64 \ build-riscv build-ppc64 build-nds32le diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6c1a7a5..d9c11ba 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -36,12 +36,11 @@ MPFR_VERSION=4.1.0 MPC_VERSION=1.2.1 GCC_VERSION=11.2.0 -GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.37 -IASL_VERSION=20210331 +IASL_VERSION=20210930 # CLANG version number -CLANG_VERSION=12.0.0 -CMAKE_VERSION=3.20.3 +CLANG_VERSION=13.0.0 +CMAKE_VERSION=3.21.4 NASM_VERSION=2.15.05 # GCC toolchain archive locations @@ -852,7 +851,6 @@ print_supported() { case "$PRINTSUPPORTED" in - AUTOCONF|autoconf) printf "%s\n" "$GCC_AUTOCONF_VERSION";; BINUTILS|binutils) printf "%s\n" "$BINUTILS_VERSION";; CLANG|clang) printf "%s\n" "$CLANG_VERSION";; GCC|gcc) printf "%s\n" "$GCC_VERSION";; diff --git a/util/crossgcc/patches/acpica-unix2-20210331_iasl.patch b/util/crossgcc/patches/acpica-unix2-20210930_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20210331_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20210930_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum deleted file mode 100644 index 1aa77c2..0000000 --- a/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -1a4006727962daf63a181c853695ca69bdf7d541 tarballs/acpica-unix2-20210331.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20210930.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20210930.tar.gz.cksum new file mode 100644 index 0000000..272f40d --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20210930.tar.gz.cksum @@ -0,0 +1 @@ +bee7a26c7b82f5d4ca6f77cd399998d054ff95a1 tarballs/acpica-unix2-20210930.tar.gz diff --git a/util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum deleted file mode 100644 index 42be5d9..0000000 --- a/util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -51250856f368acef5ab335a16f994bf29ad3d115 tarballs/clang-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-13.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-13.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..3e6c8aa --- /dev/null +++ b/util/crossgcc/sum/clang-13.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +c071f016b5e8965a52cea4f0905924aaf5495d49 tarballs/clang-13.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum deleted file mode 100644 index 6328594..0000000 --- a/util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5fe54db45be35b8f77acc32f08e01912f8e8b915 tarballs/clang-tools-extra-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-13.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-13.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..f608f98 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-13.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +7fe8345c57469fcf32945a16dc0a719e9131741c tarballs/clang-tools-extra-13.0.0.src.tar.xz diff --git a/util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum deleted file mode 100644 index 2ac43e8..0000000 --- a/util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -96e498c4d1ac238b6852b1113102bf2301bb88d8 tarballs/cmake-3.20.3.tar.gz diff --git a/util/crossgcc/sum/cmake-3.21.4.tar.gz.cksum b/util/crossgcc/sum/cmake-3.21.4.tar.gz.cksum new file mode 100644 index 0000000..a72cc15 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.21.4.tar.gz.cksum @@ -0,0 +1 @@ +7d5bde583207dc205cba158ce46f0c389884b211 tarballs/cmake-3.21.4.tar.gz diff --git a/util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum deleted file mode 100644 index 650f8e5..0000000 --- a/util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7b02a455fbc6fe395da8d5411072acc04d669d94 tarballs/compiler-rt-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-13.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-13.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..a33d640 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-13.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +f3241c200e739abbfa846c707175fd711d3cf4fe tarballs/compiler-rt-13.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum deleted file mode 100644 index e4f3aa3..0000000 --- a/util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -dbc1cf6aa2dbdeccd7ad26c9215b56963a5686d3 tarballs/llvm-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-13.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-13.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..7b8473b --- /dev/null +++ b/util/crossgcc/sum/llvm-13.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +0be63c8b3b44f3af49d9e57130f7b76a6040427c tarballs/llvm-13.0.0.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/59174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Gerrit-Change-Number: 59174 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021