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Change subject: security/vboot: Add NVRAM counter for TPM 2.0
......................................................................
Patch Set 3:
(3 comments)
Patchset:
PS3:
Thanks for the guidance, I'll try to test it on Monday when I'm at the office and can pick up a servo to disable write protection for another device.
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/59097/comment/ef459248_67ad5df2
PS3, Line 150: .TPMA_NV_NO_DA = 1,
> Actually, now that I'm comparing this more with the ZTE counter space I'm also wondering why it has […]
NV_BITS makes it a bit index which is bit different from a counter.
Not sure why we would need NO_DA, as authorization can't really fail anyways. Out of curiousity, why is it needed for ZTE?
https://review.coreboot.org/c/coreboot/+/59097/comment/54232933_b67e0f8a
PS3, Line 438: NULL, 0)
> Soo... actually, wait a second. […]
I think recreating the counter wont help an attacker, it will start again at a higher ot the same value.
From the specification:
"When an NV counter is created, the TPM shall initialize the 8-octet counter value with a number that is
greater than any count value for any NV counter on the TPM since the time of TPM manufacture."
Or am I overlooking something here?
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Change subject: util/docker/coreboot-sdk: Add bsdextrautils & lcov
......................................................................
Patch Set 1: Code-Review+2
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Change subject: arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS
......................................................................
Patch Set 2:
(1 comment)
File src/arch/x86/include/arch/smp/spinlock.h:
https://review.coreboot.org/c/coreboot/+/59021/comment/f4585196_d61553d1
PS2, Line 50: thread_coop_disable();
> Can you explain why this __always_inline is needed? (Git says it has been here since 2005 and was ad […]
For this particular __always_inline, it might be unnecessary. I just don't know. AGESA codebase had (poor) structure were stack pointers were manipulated in a way that could not retrieve return address from the stack so inlining was mandatory.
AMD family10 codebase has (well had) other issues with spinlocks and there is some ongoing effort in bringing asus/kgpe-d16 back upstream. This was mostly criticism on allowing to add non-inlined function call into function with __always_inline attribute in the first place.
A mutex with threading disabled has no other context to switch to, and behaves exactly like spinlock there. I believe Raul's proposal 1 in CB:59094 was to replace spinlocks with mutexes.
For a simple sequence, like with spin_lock(cmos_lock) where register access is not atomic but an index/data pair, I see no reason to switch to mutex, though.
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Change subject: Documentation: Remove references to "private" changes on Gerrit
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/brya/var/kano: Add thermal sensor settings
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/var/gimble: Update thermal table for Gimble
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/brya/variants/gimble/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59102/comment/c16869f1_2db601d9
PS8, Line 53: 53
I feel this temperature threshold is very low for sensor_0 which is for DRAM. This might cause early PL1 throttling and impact performance.
Can you share your side test results over bug with this CL for our reference ?
https://review.coreboot.org/c/coreboot/+/59102/comment/ab058ebe_5f1e71f2
PS8, Line 75: 0
How does it help on system performance side ? Please, share test results on bug. Thanks.
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Hello build bot (Jenkins), Hsuan Ting Chen, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Aseda Aboagye, Julius Werner, Andrey Petrov, Yu-Ping Wu, Patrick Rudolph, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58253
to look at the new patch set (#9).
Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
......................................................................
Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016.
This relands commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org>
---
M src/include/bootmode.h
M src/mainboard/emulation/qemu-q35/chromeos.c
M src/mainboard/google/asurada/chromeos.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/cherry/chromeos.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/daisy/chromeos.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/dedede/variants/baseboard/gpio.c
M src/mainboard/google/deltaur/chromeos.c
M src/mainboard/google/drallion/chromeos.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/eve/gpio.h
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/fizz/variants/karma/gpio.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/chromeos.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h
M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h
M src/mainboard/google/glados/variants/cave/include/variant/gpio.h
M src/mainboard/google/glados/variants/chell/include/variant/gpio.h
M src/mainboard/google/glados/variants/glados/include/variant/gpio.h
M src/mainboard/google/glados/variants/lars/include/variant/gpio.h
M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/hatch/variants/akemi/gpio.c
M src/mainboard/google/hatch/variants/ambassador/gpio.c
M src/mainboard/google/hatch/variants/dooly/gpio.c
M src/mainboard/google/hatch/variants/dratini/gpio.c
M src/mainboard/google/hatch/variants/duffy/gpio.c
M src/mainboard/google/hatch/variants/faffy/gpio.c
M src/mainboard/google/hatch/variants/genesis/gpio.c
M src/mainboard/google/hatch/variants/hatch/gpio.c
M src/mainboard/google/hatch/variants/helios/gpio.c
M src/mainboard/google/hatch/variants/jinlon/gpio.c
M src/mainboard/google/hatch/variants/kaisa/gpio.c
M src/mainboard/google/hatch/variants/kindred/gpio.c
M src/mainboard/google/hatch/variants/kohaku/gpio.c
M src/mainboard/google/hatch/variants/moonbuggy/gpio.c
M src/mainboard/google/hatch/variants/mushu/gpio.c
M src/mainboard/google/hatch/variants/nightfury/gpio.c
M src/mainboard/google/hatch/variants/noibat/gpio.c
M src/mainboard/google/hatch/variants/palkia/gpio.c
M src/mainboard/google/hatch/variants/puff/gpio.c
M src/mainboard/google/hatch/variants/scout/gpio.c
M src/mainboard/google/hatch/variants/stryke/gpio.c
M src/mainboard/google/hatch/variants/wyvern/gpio.c
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kukui/chromeos.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/mistral/chromeos.c
M src/mainboard/google/nyan/chromeos.c
M src/mainboard/google/nyan_big/chromeos.c
M src/mainboard/google/nyan_blaze/chromeos.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/peach_pit/chromeos.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/poppy/variants/atlas/gpio.c
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/poppy/variants/nami/gpio.c
M src/mainboard/google/poppy/variants/nautilus/gpio.c
M src/mainboard/google/poppy/variants/nocturne/gpio.c
M src/mainboard/google/poppy/variants/rammus/gpio.c
M src/mainboard/google/poppy/variants/soraka/gpio.c
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/coral/gpio.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/smaug/chromeos.c
M src/mainboard/google/storm/chromeos.c
M src/mainboard/google/trogdor/chromeos.c
M src/mainboard/google/veyron/chromeos.c
M src/mainboard/google/veyron_mickey/chromeos.c
M src/mainboard/google/veyron_rialto/chromeos.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/google/volteer/variants/collis/gpio.c
M src/mainboard/google/volteer/variants/copano/gpio.c
M src/mainboard/google/volteer/variants/halvor/gpio.c
M src/mainboard/google/volteer/variants/terrador/gpio.c
M src/mainboard/google/volteer/variants/todor/gpio.c
M src/mainboard/google/volteer/variants/voema/gpio.c
M src/mainboard/google/zork/Makefile.inc
M src/mainboard/google/zork/chromeos.c
M src/mainboard/google/zork/variants/baseboard/Makefile.inc
D src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/kunimitsu/gpio.h
M src/mainboard/intel/shadowmountain/chromeos.c
M src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/security/vboot/bootmode.c
M src/security/vboot/vboot_logic.c
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/skylake/Makefile.inc
115 files changed, 541 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/58253/9
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Change subject: mb/google/brya/variants/gimble: Update PL1 min value
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Thanks Scott for this review.
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Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
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Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
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Gerrit-CC: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com>
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Gerrit-Comment-Date: Fri, 12 Nov 2021 04:17:19 +0000
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