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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Paul Menzel, Julius Werner, Angel Pons, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57861
to look at the new patch set (#12).
Change subject: Documentation/RFC: Generalize PCI support in coreboot
......................................................................
Documentation/RFC: Generalize PCI support in coreboot
Design Doc describing how we would refactor the mmio accesses in the
PCI config space in coreboot so that we can extend the support to
platforms that do not support ECAM.
BUG=b:181098581
BRANCH=None
TEST=None
Change-Id: I3a56d932f6e047087c38a7687564065cc1562363
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
A Documentation/RFC/pci_config_access.md
A Documentation/RFC/sys_mem_map.jpg
2 files changed, 212 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/57861/12
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58580 )
Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme
......................................................................
Patch Set 5:
(1 comment)
File src/soc/qualcomm/common/gpio.c:
https://review.coreboot.org/c/coreboot/+/58580/comment/a33616d6_13f181af
PS2, Line 21: if ((read32(®s->cfg) >> GPIO_EGPIO_SHFT) & GPIO_EGPIO_BMSK)
> I might be missing something here, but we want to set the 12th bit only in case the 11th bit (eGPIO_ […]
Would this work?
| (read32(®s->cfg) & GPIO_EGPIO_BMSK) << GPIO_EGPIO_SHFT)
Where:
GPIO_EGPIO_BMSK = BIT(11)
GPIO_EGPIO_SHFT = 1
Basically bitwise and to see if bit 11 is set and if it is, left shift by 1 to set bit 12. If bit 11 isn't set, the bitwise OR won't end up changing any bits.
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 )
Change subject: soc/intel/common: add generic gpio lock mechanism
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/58351/comment/33b4c27e_b42f91b9
PS7, Line 461: int gpio_lock_multiple_pads(const struct gpio_lock_config *pads_a, const size_t count_a,
: const struct gpio_lock_config *pads_b, const size_t count_b)
> As it stands in latest patchset, total time is under 2ms : […]
The list concat approach took 1972 uSec :
finalize: soc_lock_gpio took 1972 uSec
Let's stick with the calling it twice approach in the current patchset.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59125 )
Change subject: acpi/acpigen,soc/amd,cpu/inte: Refactor the code
......................................................................
Patch Set 1:
(1 comment)
File src/acpi/acpigen.c:
https://review.coreboot.org/c/coreboot/+/59125/comment/346d2174_f14db5fc
PS1, Line 1808: __weak void acpigen_write_CPPC_method(int core_id)
i'm not exactly sure what the goal of this change will be, but i'd avoid using weak functions if possible, since having weak functions where it would be avoidable might hide bugs like this one CB:58662
if there's some functionality needed to generate sufficiently different acpi code for a similar purpose, i'd either create another function for that or maybe add some sort of parameter to enable the generation of the additional acpi code
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Change subject: soc/intel/alderlake: Disable VT-d for early silicons
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/59191/comment/e7eb7327_c6de8c8a
PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1
> Ooph my eyes are broken today, thanks Felix 😄 […]
Looks good to me 😊
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