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Change subject: utils: Add initial version of "remove_unused_code" script
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Raul, When you have the time, could you do a review of the bash?
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Change subject: drivers/wifi/generic: fix package_size to align with WLAN driver
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
@Tim, any comments?
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Change subject: drivers/wifi/generic: fix package_size to align with WLAN driver
......................................................................
Patch Set 6:
(3 comments)
Patchset:
PS6:
> Sorry, for the DSM format, this value is come from the SAR table itself, not form the CONFIG. […]
Hi Eric,
This CL is for EWRD, which is for 2nd, 3rd and 4th SAR table content writing into ACPI, nothing about DSM here.
PS6:
> @Matt, I found the bug is from https://chromium-review.googlesource. […]
Hi Eric,
This is viable to fix that tool issue. I agree to fix that as well.
But I'd like to raise there are 2 ADL-P projects are done 6E SAR validation with this CL, if we request them to apply from tool fix and drop this CL in CB, they will be likely to walk through SAR validation again, which may cost more than they expect. This is for business purpose consideration.
PS6:
> I wonder there is some bug when fill SAR table from the cbfs file.
Maybe, I am not clear since I was not involved for the developing codes process.
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Change subject: soc/intel/tigerlake: Add config option for S3 ACPI
......................................................................
Patch Set 17: Code-Review+1
(1 comment)
File src/soc/intel/tigerlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/59024/comment/f9ea4383_45912a59
PS17, Line 282: } Else {
one more tab here
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Change subject: util/lint: Exclude coreboot-configurator directory from checkpatch
......................................................................
Patch Set 2:
(1 comment)
File util/lint/lint-extended-007-checkpatch:
https://review.coreboot.org/c/coreboot/+/59096/comment/51d3dd74_a1727263
PS2, Line 15: util/coreboot-configurator
You don't want to add it here, this is a list of directories TO run checkpatch on.
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Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/brya/variants/primus/variant.c:
https://review.coreboot.org/c/coreboot/+/59135/comment/302b5997_66ac5982
PS5, Line 3: #include <console/console.h>
> unused?
Done
https://review.coreboot.org/c/coreboot/+/59135/comment/eea0bef2_9d1dd7d4
PS5, Line 6: #include <soc/pci_devs.h>
> unused?
Done
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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
Patch Set 32:
(2 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/56773/comment/2b6bda5c_744ea72b
PS32, Line 237:
not directly related to this patch: would be good to have the .subprog = 0 assignment explicitly for consistency
https://review.coreboot.org/c/coreboot/+/56773/comment/c0e35255_3bfef837
PS32, Line 271: { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
: { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
not directly related to this patch: these two entries seem to be duplicates of entries above. is this needed on any platform?
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Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature
......................................................................
Patch Set 32:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/56773/comment/74cd6184_0830f9b5
PS32, Line 804: if (count > MAX_PSP_ENTRIES) {
: fprintf(stderr, "Error: PSP entries exceed max allowed items\n");
: free(ctx->rom);
: exit(1);
: }
this block should be replaced with a call to assert_fw_entry right before the pspdir->entries[count] accesses
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