Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59244 )
Change subject: soc/mediatek: change help text of FLASH_DUAL_READ
......................................................................
soc/mediatek: change help text of FLASH_DUAL_READ
Change help text to "dual IO read mode" to reduce noun confusion.
Suggestion from this comment:
https://review.coreboot.org/c/coreboot/+/58837/comment/40a98af1_dce6bb2b/
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I54b81cdeba3b693451f66e003fb470c9f8c19ad9
---
M src/soc/mediatek/mt8186/Kconfig
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8195/Kconfig
3 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/59244/1
diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig
index 1821fa9..9b8708a 100644
--- a/src/soc/mediatek/mt8186/Kconfig
+++ b/src/soc/mediatek/mt8186/Kconfig
@@ -21,6 +21,6 @@
default y
help
When this option is enabled, the flash controller provides the ability
- to dual read mode.
+ to dual IO read mode.
endif
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index e099ffd..9b55295 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -55,7 +55,7 @@
default y
help
When this option is enabled, the flash controller provides the ability
- to dual read mode.
+ to dual IO read mode.
config SRCLKEN_RC_SUPPORT
bool
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig
index b96ccd8..d1cb09b 100644
--- a/src/soc/mediatek/mt8195/Kconfig
+++ b/src/soc/mediatek/mt8195/Kconfig
@@ -54,6 +54,6 @@
default y
help
When this option is enabled, the flash controller provides the ability
- to dual read mode.
+ to dual IO read mode.
endif
--
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EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59243 )
Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6
......................................................................
mb/google/brya/var/felwinter: Disable PCIE port 6
PCIE port 6 is empty as shcematics.
BUG=b:206047996
TEST=PCIE port 6 is disabled.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/59243/1
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 4647551..ad470a8 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -59,6 +59,7 @@
end
end
end
+ device ref pcie_rp6 off end
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
--
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Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59242 )
Change subject: mb/google/brya: Create vell variant
......................................................................
mb/google/brya: Create vell variant
Create the vell variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:205908918
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_VELL
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/vell/include/variant/ec.h
A src/mainboard/google/brya/variants/vell/include/variant/gpio.h
A src/mainboard/google/brya/variants/vell/memory/Makefile.inc
A src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/vell/overridetree.cb
8 files changed, 45 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/59242/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 850a78c..70729c9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -103,6 +103,7 @@
default "Taeko" if BOARD_GOOGLE_TAEKO
default "Felwinter" if BOARD_GOOGLE_FELWINTER
default "Anahera" if BOARD_GOOGLE_ANAHERA
+ default "Vell" if BOARD_GOOGLE_VELL
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -114,6 +115,7 @@
default "taeko" if BOARD_GOOGLE_TAEKO
default "felwinter" if BOARD_GOOGLE_FELWINTER
default "anahera" if BOARD_GOOGLE_ANAHERA
+ default "vell" if BOARD_GOOGLE_VELL
config DIMM_SPD_SIZE
default 512
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 8d58fa5..bd8cf6f 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -67,3 +67,7 @@
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GFX_GENERIC
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+config BOARD_GOOGLE_VELL
+ bool "-> Vell"
+ select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/vell/include/variant/ec.h b/src/mainboard/google/brya/variants/vell/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
new file mode 100644
index 0000000..6751a42
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9621137
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
--
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Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )
Change subject: soc/intel/alderlake: Disable VT-d for early silicons
......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/59191/comment/d61c9e0b_8d51e4d0
PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1
> Looks good to me 😊
Thanks :) Done!
https://review.coreboot.org/c/coreboot/+/59191/comment/1d973893_14602ffe
PS3, Line 268: m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS;
> nit: blank line after […]
Done
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Hello Abhijeet Rao, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Disable VT-d for early silicons
......................................................................
soc/intel/alderlake: Disable VT-d for early silicons
VT-d needs to disabled for early silicons as it results in a
CPU hard hang.
BUG=b:197177091
Test=Boot brya to OS with no hang
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59191/5
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Hello Abhijeet Rao, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Disable VT-d for early silicons
......................................................................
soc/intel/alderlake: Disable VT-d for early silicons
VT-d needs to disabled for early silicons as it results in a
CPU hard hang.
BUG=b:197177091
Test=Boot brya to OS with no hang
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59191/4
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59134 )
Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
......................................................................
Patch Set 2: Code-Review+2
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Hello Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel/../thermal: Refactor PCH Thermal Configuration common API
......................................................................
soc/intel/../thermal: Refactor PCH Thermal Configuration common API
Thermal configuration has evolved over PCH generations where
latest PCH has provided an option to allow thermal configuration
using PMC PWRMBASE registers.
This patch adds an option for impacted SoC to select the Kconfig
for allowing thermal configuration using PMC PCH MMIO space.
TODO: Combine all changes for now till we split it meaningfully.
BUG=b:193774296
Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/common/block/thermal/Kconfig
M src/soc/intel/common/block/thermal/thermal.c
3 files changed, 41 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/3
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