coreboot-gerrit November 2021

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Change in coreboot[master]: soc/mediatek/mt8186: Add support for regulator VMCH and VMC
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59254 ) Change subject: soc/mediatek/mt8186: Add support for regulator VMCH and VMC ...................................................................... soc/mediatek/mt8186: Add support for regulator VMCH and VMC Add support for VMCH and VMC of MT6366. TEST=measure voltage 3.3V for VMCH and VMC BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb --- M src/soc/mediatek/mt8186/include/soc/mt6366.h M src/soc/mediatek/mt8186/mt6366.c 2 files changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/59254/1 diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h index ef711c9..6f35249 100644 --- a/src/soc/mediatek/mt8186/include/soc/mt6366.h +++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h @@ -37,7 +37,13 @@ PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, PMIC_VDDQ_OP_EN = 0x1b16, + PMIC_LDO_VMC_CON0 = 0x1cc4, + PMIC_LDO_VMC_OP_EN = 0x1cc6, + PMIC_LDO_VMCH_CON0 = 0x1cd8, + PMIC_LDO_VMCH_OP_EN = 0x1cda, PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VMCH_ANA_CON0 = 0x1e48, + PMIC_VMC_ANA_CON0 = 0x1e4c, PMIC_VDDQ_ELR_0 = 0x1ec4, }; @@ -45,6 +51,8 @@ MT6366_VCORE = 0, MT6366_VDRAM1, MT6366_VDDQ, + MT6366_VMCH, + MT6366_VMC, MT6366_REGULATOR_NUM, }; diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 40d31e5..1fabcf4 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -560,6 +560,112 @@ udelay(1); } +static u32 pmic_get_vmch_vol(void) +{ + u32 vol_reg, ret; + + vol_reg = pwrap_read_field(PMIC_VMCH_ANA_CON0, 0x7, 8); + + switch (vol_reg) { + case 2: + ret = 2900000; + break; + case 3: + ret = 3000000; + break; + case 5: + ret = 3300000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VMCH read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vmch_vol(u32 vmch_uv) +{ + u32 val = 0; + + switch (vmch_uv) { + case 2900000: + val = 2; + break; + case 3000000: + val = 3; + break; + case 3300000: + val = 5; + break; + default: + die("ERROR[%s]: VMCH voltage %u is not support.\n", __func__, vmch_uv); + return; + } + + pwrap_write_field(PMIC_VMCH_ANA_CON0, val, 0x7, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VMCH_OP_EN, 1, 0xFF, 0); + pwrap_write_field(PMIC_LDO_VMCH_CON0, 1, 0xFF, 0); +} + +static u32 pmic_get_vmc_vol(void) +{ + u32 vol_reg, ret; + + vol_reg = pwrap_read_field(PMIC_VMC_ANA_CON0, 0xF, 8); + + switch (vol_reg) { + case 0x4: + ret = 1800000; + break; + case 0xA: + ret = 2900000; + break; + case 0xB: + ret = 3000000; + break; + case 0xD: + ret = 3300000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VMC read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vmc_vol(u32 vmc_uv) +{ + u32 val = 0; + + switch (vmc_uv) { + case 1800000: + val = 0x4; + break; + case 2900000: + val = 0xA; + break; + case 3000000: + val = 0xB; + break; + case 3300000: + val = 0xD; + break; + default: + die("ERROR[%s]: VMC voltage %u is not support.\n", __func__, vmc_uv); + return; + } + + pwrap_write_field(PMIC_VMC_ANA_CON0, val, 0xF, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VMC_OP_EN, 1, 0xFF, 0); + pwrap_write_field(PMIC_LDO_VMC_CON0, 1, 0xFF, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ @@ -667,6 +773,12 @@ case MT6366_VDDQ: pmic_set_vddq_vol(voltage_uv); break; + case MT6366_VMCH: + pmic_set_vmch_vol(voltage_uv); + break; + case MT6366_VMC: + pmic_set_vmc_vol(voltage_uv); + break; default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; @@ -682,6 +794,10 @@ return pmic_get_vdram1_vol(); case MT6366_VDDQ: return pmic_get_vddq_vol(); + case MT6366_VMCH: + return pmic_get_vmch_vol(); + case MT6366_VMC: + return pmic_get_vmc_vol(); default: printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/59254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb Gerrit-Change-Number: 59254 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Add AUXADC driver support
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59253 ) Change subject: soc/mediatek/mt8186: Add AUXADC driver support ...................................................................... soc/mediatek/mt8186: Add AUXADC driver support Add AUXADC controller driver code. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/include/soc/auxadc.h A src/soc/mediatek/mt8186/include/soc/efuse.h 3 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/59253/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 4c89f3d..7d6d2ff 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) +bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c @@ -12,6 +13,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c +verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -19,6 +21,7 @@ verstage-y += ../common/uart.c verstage-y += ../common/wdt.c wdt.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/flash_controller.c @@ -30,6 +33,7 @@ romstage-y += ../common/wdt.c wdt.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +ramstage-y += ../common/auxadc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8186/include/soc/auxadc.h b/src/soc/mediatek/mt8186/include/soc/auxadc.h new file mode 100644 index 0000000..13a52e3 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/auxadc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_AUXADC_H +#define SOC_MEDIATEK_MT8186_AUXADC_H + +#include <soc/auxadc_common.h> +#include <soc/infracfg.h> +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8186_infracfg_ao_regs *const mtk_infracfg = mt8186_infracfg_ao; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/efuse.h b/src/soc/mediatek/mt8186/include/soc/efuse.h new file mode 100644 index 0000000..fe3dfff --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_EFUSE_H +#define SOC_MEDIATEK_MT8186_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t reserved[130]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x208); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f Gerrit-Change-Number: 59253 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: add GIC pre-initialization function
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59252 ) Change subject: soc/mediatek/mt8186: add GIC pre-initialization function ...................................................................... soc/mediatek/mt8186: add GIC pre-initialization function GIC(generic interrupt controller) defines architectural requirements for handling all interrupt sources and common interrupt controller programming interface. GIC needs to be pre-initialized on MT8186, so we add this initialize function. TEST=build pass BUG=b:202871018 Change-Id: I6bf439d0d9e1ca7130a69b9006b957afca8b133c Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/bootblock.c A src/soc/mediatek/mt8186/gic.c A src/soc/mediatek/mt8186/include/soc/gic.h 4 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59252/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 37c1b3c..4c89f3d 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c +bootblock-y += gic.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c index 17fd27e..d5b288a 100644 --- a/src/soc/mediatek/mt8186/bootblock.c +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/eint_event.h> +#include <soc/gic.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/wdt.h> @@ -12,4 +13,5 @@ mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); + mtk_gic_preinit(); } diff --git a/src/soc/mediatek/mt8186/gic.c b/src/soc/mediatek/mt8186/gic.c new file mode 100644 index 0000000..ac07764 --- /dev/null +++ b/src/soc/mediatek/mt8186/gic.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.3 + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gic.h> + +void mtk_gic_preinit(void) +{ + int i; + + for (i = 3; i < 15; i++) { + write32((void *)((uintptr_t)MCUSYS_BASE + 0xA600 + i * 4), 0); + write32((void *)((uintptr_t)MCUSYS_BASE + 0xA650 + i * 4), 0xFFFFFFFF); + } +} diff --git a/src/soc/mediatek/mt8186/include/soc/gic.h b/src/soc/mediatek/mt8186/include/soc/gic.h new file mode 100644 index 0000000..7e11107 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/gic.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.3 + */ + +#ifndef SOC_MEDIATEK_MT8186_GIC_H +#define SOC_MEDIATEK_MT8186_GIC_H + +void mtk_gic_preinit(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bf439d0d9e1ca7130a69b9006b957afca8b133c Gerrit-Change-Number: 59252 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: add USB support
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59251 ) Change subject: soc/mediatek/mt8186: add USB support ...................................................................... soc/mediatek/mt8186: add USB support 1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 --- M src/mainboard/google/corsola/mainboard.c M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/usb.h A src/soc/mediatek/mt8186/usb.c 5 files changed, 58 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59251/1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index e6040fa..195ce67 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/usb.h> static void mainboard_init(struct device *dev) { + setup_usb_host(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 2107ab8..37c1b3c 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/wdt.c wdt.c ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index 28ba369..cabafb6 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -64,9 +64,11 @@ SPI5_BASE = IO_PHYS + 0x01015000, I2C5_BASE = IO_PHYS + 0x01016000, I2C9_BASE = IO_PHYS + 0x01019000, - SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, + /* Corsola uses USB2 port1 instead of USB2 port0. */ + SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00, MSDC0_BASE = IO_PHYS + 0x01230000, - SSUSB_SIF_BASE = IO_PHYS + 0x01CA0000, + /* Corsola uses USB2 port1 instead of USB2 port0. */ + SSUSB_SIF_BASE = IO_PHYS + 0x01C80300, EFUSEC_BASE = IO_PHYS + 0x01CB0000, MIPITX_BASE = IO_PHYS + 0x01CC0000, MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, diff --git a/src/soc/mediatek/mt8186/include/soc/usb.h b/src/soc/mediatek/mt8186/include/soc/usb.h new file mode 100644 index 0000000..297c8f1 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/usb.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_USB_H +#define SOC_MEDIATEK_MT8186_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64 * 5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 1 + +#endif diff --git a/src/soc/mediatek/mt8186/usb.c b/src/soc/mediatek/mt8186/usb.c new file mode 100644 index 0000000..328dc54 --- /dev/null +++ b/src/soc/mediatek/mt8186/usb.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.5 + */ + +#include <device/mmio.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/usb.h> + +static void usb3_hub_reset(void) +{ + gpio_output(GPIO(PERIPHERAL_EN2), 1); +} + +void mtk_usb_prepare(void) +{ + usb3_hub_reset(); + gpio_output(GPIO(USB_DRVVBUS_P1), 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Gerrit-Change-Number: 59251 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Implement regulator interface
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59250 ) Change subject: mb/google/corsola: Implement regulator interface ...................................................................... mb/google/corsola: Implement regulator interface Use regulator interface to use regulator more easily. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b --- M src/mainboard/google/corsola/Makefile.inc A src/mainboard/google/corsola/regulator.c M src/soc/mediatek/common/include/soc/regulator.h 3 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/59250/1 diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 4720dc5..7995f8a 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -8,9 +8,11 @@ romstage-y += memlayout.ld romstage-y += chromeos.c +romstage-y += regulator.c romstage-y += romstage.c ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c +ramstage-y += regulator.c ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/regulator.c b/src/mainboard/google/corsola/regulator.c new file mode 100644 index 0000000..1ddc52c --- /dev/null +++ b/src/mainboard/google/corsola/regulator.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <soc/mt6366.h> +#include <soc/regulator.h> + +#define REGULATOR_NOT_SUPPORT -1 + +static const int regulator_id[] = { + [MTK_REGULATOR_VDD1] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VDD2] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VDDQ] = MT6366_VDDQ, + [MTK_REGULATOR_VMDDR] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VCORE] = MT6366_VCORE, + [MTK_REGULATOR_VCC] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VCCQ] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VDRAM1] = MT6366_VDRAM1, +}; + +_Static_assert(ARRAY_SIZE(regulator_id) == MTK_REGULATOR_NUM, "regulator_id size error"); + +void mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv) +{ + assert(regulator < MTK_REGULATOR_NUM); + + if (regulator_id[regulator] < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return; + } + mt6366_set_voltage(regulator_id[regulator], voltage_uv); +} + +uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator) +{ + assert(regulator < MTK_REGULATOR_NUM); + + if (regulator_id[regulator] < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return 0; + } + return mt6366_get_voltage(regulator_id[regulator]); +} diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 0cd0f1e..08ce47f 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -13,12 +13,13 @@ MTK_REGULATOR_VCORE, MTK_REGULATOR_VCC, MTK_REGULATOR_VCCQ, + MTK_REGULATOR_VDRAM1, + MTK_REGULATOR_NUM, }; void mainboard_set_regulator_vol(enum mtk_regulator regulator, uint32_t voltage_uv); uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator); - int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable); uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator); -- To view, visit https://review.coreboot.org/c/coreboot/+/59250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b Gerrit-Change-Number: 59250 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: add configuration for kingler and krabby
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59249 ) Change subject: mb/google/corsola: add configuration for kingler and krabby ...................................................................... mb/google/corsola: add configuration for kingler and krabby The 'corsola' reference design will include two implementations with different BOM selections - 'krabby' and 'kingler'. TEST=none BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59249/1 diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index bfdc8ee..f8906d6 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -22,6 +22,8 @@ config MAINBOARD_PART_NUMBER string default "Corsola" if BOARD_GOOGLE_CORSOLA + default "Kingler" if BOARD_GOOGLE_KINGLER + default "Krabby" if BOARD_GOOGLE_KRABBY config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index 3b44019..baeb67a 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -3,3 +3,11 @@ config BOARD_GOOGLE_CORSOLA bool "-> Corsola" select BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_GOOGLE_KINGLER + bool "-> Kingler" + select BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_GOOGLE_KRABBY + bool "-> Krabby" + select BOARD_GOOGLE_CORSOLA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/59249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb Gerrit-Change-Number: 59249 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: add SPM register definitions
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59248 ) Change subject: soc/mediatek/mt8186: add SPM register definitions ...................................................................... soc/mediatek/mt8186: add SPM register definitions Add SPM register definitions so that other drivers can use them. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Iec2b493e464be9d617226cc8a9875ee3ddb759de --- A src/soc/mediatek/mt8186/include/soc/spm.h 1 file changed, 533 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59248/1 diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h new file mode 100644 index 0000000..5ab11ea --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -0,0 +1,533 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_SPM_H +#define SOC_MEDIATEK_MT8186_SPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mtk_spm_regs { + uint32_t poweron_config_en; + uint32_t spm_power_on_val0; + uint32_t spm_power_on_val1; + uint32_t spm_clk_con; + uint32_t spm_clk_settle; + uint32_t spm_ap_standby_con; + uint32_t pcm_con0; + uint32_t pcm_con1; + uint32_t spm_power_on_val2; + uint32_t spm_power_on_val3; + uint32_t pcm_reg_data_ini; + uint32_t pcm_pwr_io_en; + uint32_t pcm_timer_val; + uint32_t pcm_wdt_val; + uint8_t reserved0[8]; + uint32_t spm_sw_rst_con; + uint32_t spm_sw_rst_con_set; + uint32_t spm_sw_rst_con_clr; + uint32_t spm_src6_mask; + uint8_t reserved1[52]; + uint32_t md32_clk_con; + uint32_t spm_sram_rsv_con; + uint32_t spm_swint; + uint32_t spm_swint_set; + uint32_t spm_swint_clr; + uint32_t spm_scp_mailbox; + uint32_t scp_spm_mailbox; + uint32_t spm_wakeup_event_sens; + uint32_t spm_wakeup_event_clear; + uint8_t reserved2[4]; + uint32_t spm_scp_irq; + uint32_t spm_cpu_wakeup_event; + uint32_t spm_irq_mask; + uint32_t spm_src_req; + uint32_t spm_src_mask; + uint32_t spm_src2_mask; + uint32_t spm_src3_mask; + uint32_t spm_src4_mask; + uint32_t spm_src5_mask; + uint32_t spm_wakeup_event_mask; + uint32_t spm_wakeup_event_ext_mask; + uint32_t spm_src7_mask; + uint32_t scp_clk_con; + uint32_t pcm_debug_con; + uint8_t reserved3[4]; + uint32_t ddren_dbc_con; + uint32_t spm_resource_ack_con4; + uint32_t spm_resource_ack_con0; + uint32_t spm_resource_ack_con1; + uint32_t spm_resource_ack_con2; + uint32_t spm_resource_ack_con3; + uint32_t pcm_reg0_data; + uint32_t pcm_reg2_data; + uint32_t pcm_reg6_data; + uint32_t pcm_reg7_data; + uint32_t pcm_reg13_data; + uint32_t src_req_sta_0; + uint32_t src_req_sta_1; + uint32_t src_req_sta_2; + uint32_t pcm_timer_out; + uint32_t pcm_wdt_out; + uint32_t spm_irq_sta; + uint32_t src_req_sta_4; + uint32_t md32pcm_wakeup_sta; + uint32_t md32pcm_event_sta; + uint32_t spm_wakeup_sta; + uint32_t spm_wakeup_ext_sta; + uint32_t spm_wakeup_misc; + uint32_t mm_dvfs_halt; + uint8_t reserved4[8]; + uint32_t bus_protect_rdy; + uint32_t bus_protect1_rdy; + uint32_t bus_protect2_rdy; + uint32_t bus_protect3_rdy; + uint32_t subsys_idle_sta; + uint32_t pcm_sta; + uint32_t src_req_sta_3; + uint32_t pwr_status; + uint32_t pwr_status_2nd; + uint32_t cpu_pwr_status; + uint32_t other_pwr_status; + uint32_t spm_vtcxo_event_count_sta; + uint32_t spm_infra_event_count_sta; + uint32_t spm_vrf18_event_count_sta; + uint32_t spm_apsrc_event_count_sta; + uint32_t spm_ddren_event_count_sta; + uint32_t md32pcm_sta; + uint32_t md32pcm_pc; + uint8_t reserved5[12]; + uint32_t dvfsrc_event_sta; + uint32_t bus_protect4_rdy; + uint32_t bus_protect5_rdy; + uint32_t bus_protect6_rdy; + uint32_t bus_protect7_rdy; + uint32_t bus_protect8_rdy; + uint8_t reserved6[20]; + uint32_t spm_twam_last_sta0; + uint32_t spm_twam_last_sta1; + uint32_t spm_twam_last_sta2; + uint32_t spm_twam_last_sta3; + uint32_t spm_twam_curr_sta0; + uint32_t spm_twam_curr_sta1; + uint32_t spm_twam_curr_sta2; + uint32_t spm_twam_curr_sta3; + uint32_t spm_twam_timer_out; + uint32_t spm_cg_check_sta; + uint32_t spm_dvfs_sta; + uint32_t spm_dvfs_opp_sta; + uint32_t spm_mcusys_pwr_con; + uint32_t spm_cputop_pwr_con; + uint32_t spm_cpu0_pwr_con; + uint32_t spm_cpu1_pwr_con; + uint32_t spm_cpu2_pwr_con; + uint32_t spm_cpu3_pwr_con; + uint32_t spm_cpu4_pwr_con; + uint32_t spm_cpu5_pwr_con; + uint32_t spm_cpu6_pwr_con; + uint32_t spm_cpu7_pwr_con; + uint8_t reserved7[4]; + uint32_t armpll_clk_con; + uint32_t mcusys_idle_sta; + uint32_t gic_wakeup_sta; + uint32_t cpu_spare_con; + uint32_t cpu_spare_con_set; + uint32_t cpu_spare_con_clr; + uint32_t armpll_clk_sel; + uint32_t ext_int_wakeup_req; + uint32_t ext_int_wakeup_req_set; + uint32_t ext_int_wakeup_req_clr; + uint8_t reserved8[12]; + uint32_t cpu_irq_mask; + uint32_t cpu_irq_mask_set; + uint32_t cpu_irq_mask_clr; + uint8_t reserved9[20]; + uint32_t cpu_wfi_en; + uint32_t cpu_wfi_en_set; + uint32_t cpu_wfi_en_clr; + uint8_t reserved10[20]; + uint32_t root_cputop_addr; + uint32_t root_core_addr; + uint8_t reserved11[40]; + uint32_t spm2sw_mailbox_0; + uint32_t spm2sw_mailbox_1; + uint32_t spm2sw_mailbox_2; + uint32_t spm2sw_mailbox_3; + uint32_t sw2spm_wakeup; + uint32_t sw2spm_wakeup_set; + uint32_t sw2spm_wakeup_clr; + uint32_t sw2spm_mailbox_0; + uint32_t sw2spm_mailbox_1; + uint32_t sw2spm_mailbox_2; + uint32_t sw2spm_mailbox_3; + uint32_t sw2spm_cfg; + uint32_t md1_pwr_con; + uint32_t conn_pwr_con; + uint32_t mfg0_pwr_con; + uint32_t mfg1_pwr_con; + uint32_t mfg2_pwr_con; + uint32_t mfg3_pwr_con; + uint32_t mfg4_pwr_con; + uint32_t mfg5_pwr_con; + uint32_t mfg6_pwr_con; + uint32_t ifr_pwr_con; + uint32_t ifr_sub_pwr_con; + uint32_t dpy_pwr_con; + uint32_t dramc_md32_pwr_con; + uint32_t isp_pwr_con; + uint32_t isp2_pwr_con; + uint32_t ipe_pwr_con; + uint32_t vde_pwr_con; + uint32_t vde2_pwr_con; + uint32_t ven_pwr_con; + uint32_t ven_core1_pwr_con; + uint32_t mdp_pwr_con; + uint32_t dis_pwr_con; + uint32_t audio_pwr_con; + uint32_t cam_pwr_con; + uint32_t cam_rawa_pwr_con; + uint32_t cam_rawb_pwr_con; + uint32_t cam_rawc_pwr_con; + uint32_t sysram_con; + uint32_t sysrom_con; + uint32_t sspm_sram_con; + uint32_t scp_sram_con; + uint32_t dpy_shu_sram_con; + uint32_t ufs_sram_con; + uint32_t devapc_ifr_sram_con; + uint32_t devapc_subifr_sram_con; + uint32_t devapc_acp_sram_con; + uint32_t usb_sram_con; + uint32_t dummy_sram_con; + uint32_t md_ext_buck_iso_con; + uint32_t ext_buck_iso; + uint32_t dxcc_sram_con; + uint32_t msdc_pwr_con; + uint32_t debugtop_sram_con; + uint32_t dp_tx_pwr_con; + uint32_t dpmaif_sram_con; + uint32_t dpy_shu2_sram_con; + uint32_t dramc_mcu2_sram_con; + uint32_t dramc_mcu_sram_con; + uint32_t mcupm_pwr_con; + uint32_t dpy2_pwr_con; + uint32_t spm_sram_con; + uint8_t reserved12[4]; + uint32_t peri_pwr_con; + uint32_t nna0_pwr_con; + uint32_t nna1_pwr_con; + uint32_t nna2_pwr_con; + uint32_t nna_pwr_con; + uint32_t adsp_pwr_con; + uint32_t dpy_sram_con; + uint32_t nna3_pwr_con; + uint8_t reserved13[8]; + uint32_t wpe_pwr_con; + uint8_t reserved14[4]; + uint32_t spm_mem_ck_sel; + uint32_t spm_bus_protect_mask_b; + uint32_t spm_bus_protect1_mask_b; + uint32_t spm_bus_protect2_mask_b; + uint32_t spm_bus_protect3_mask_b; + uint32_t spm_bus_protect4_mask_b; + uint32_t spm_emi_bw_mode; + uint32_t ap2md_peer_wakeup; + uint32_t ulposc_con; + uint32_t spm2mm_con; + uint32_t spm_bus_protect5_mask_b; + uint32_t spm2mcupm_con; + uint32_t ap_mdsrc_req; + uint32_t spm2emi_enter_ulpm; + uint32_t spm2md_dvfs_con; + uint32_t md2spm_dvfs_con; + uint32_t spm_bus_protect6_mask_b; + uint32_t spm_bus_protect7_mask_b; + uint32_t spm_bus_protect8_mask_b; + uint32_t spm_pll_con; + uint32_t rc_spm_ctrl; + uint32_t spm_dram_mcu_sw_con_0; + uint32_t spm_dram_mcu_sw_con_1; + uint32_t spm_dram_mcu_sw_con_2; + uint32_t spm_dram_mcu_sw_con_3; + uint32_t spm_dram_mcu_sw_con_4; + uint32_t spm_dram_mcu_sta_0; + uint32_t spm_dram_mcu_sta_1; + uint32_t spm_dram_mcu_sta_2; + uint32_t spm_dram_mcu_sw_sel_0; + uint32_t relay_dvfs_level; + uint8_t reserved15[4]; + uint32_t dramc_dpy_clk_sw_con_0; + uint32_t dramc_dpy_clk_sw_con_1; + uint32_t dramc_dpy_clk_sw_con_2; + uint32_t dramc_dpy_clk_sw_con_3; + uint32_t dramc_dpy_clk_sw_sel_0; + uint32_t dramc_dpy_clk_sw_sel_1; + uint32_t dramc_dpy_clk_sw_sel_2; + uint32_t dramc_dpy_clk_sw_sel_3; + uint32_t dramc_dpy_clk_spm_con; + uint32_t spm_dvfs_level; + uint32_t spm_cirq_con; + uint32_t spm_dvfs_misc; + uint8_t reserved16[4]; + uint32_t rg_module_sw_cg_0_mask_req_0; + uint32_t rg_module_sw_cg_0_mask_req_1; + uint32_t rg_module_sw_cg_0_mask_req_2; + uint32_t rg_module_sw_cg_1_mask_req_0; + uint32_t rg_module_sw_cg_1_mask_req_1; + uint32_t rg_module_sw_cg_1_mask_req_2; + uint32_t rg_module_sw_cg_2_mask_req_0; + uint32_t rg_module_sw_cg_2_mask_req_1; + uint32_t rg_module_sw_cg_2_mask_req_2; + uint32_t rg_module_sw_cg_3_mask_req_0; + uint32_t rg_module_sw_cg_3_mask_req_1; + uint32_t rg_module_sw_cg_3_mask_req_2; + uint32_t pwr_status_mask_req_0; + uint32_t pwr_status_mask_req_1; + uint32_t pwr_status_mask_req_2; + uint32_t spm_cg_check_con; + uint32_t spm_src_rdy_sta; + uint32_t spm_dvs_dfs_level; + uint32_t spm_force_dvfs; + uint8_t reserved17[256]; + uint32_t spm_sw_flag_0; + uint32_t spm_sw_debug_0; + uint32_t spm_sw_flag_1; + uint32_t spm_sw_debug_1; + uint32_t spm_sw_rsv_0; + uint32_t spm_sw_rsv_1; + uint32_t spm_sw_rsv_2; + uint32_t spm_sw_rsv_3; + uint32_t spm_sw_rsv_4; + uint32_t spm_sw_rsv_5; + uint32_t spm_sw_rsv_6; + uint32_t spm_sw_rsv_7; + uint32_t spm_sw_rsv_8; + uint32_t spm_bk_wake_event; + uint32_t spm_bk_vtcxo_dur; + uint32_t spm_bk_wake_misc; + uint32_t spm_bk_pcm_timer; + uint8_t reserved18[12]; + uint32_t spm_rsv_con_0; + uint32_t spm_rsv_con_1; + uint32_t spm_rsv_sta_0; + uint32_t spm_rsv_sta_1; + uint32_t spm_spare_con; + uint32_t spm_spare_con_set; + uint32_t spm_spare_con_clr; + uint32_t spm_cross_wake_m00_req; + uint32_t spm_cross_wake_m01_req; + uint32_t spm_cross_wake_m02_req; + uint32_t spm_cross_wake_m03_req; + uint32_t scp_vcore_level; + uint32_t sc_mm_ck_sel_con; + uint32_t spare_ack_mask; + uint32_t spm_spare_function; + uint32_t spm_dv_con_0; + uint32_t spm_dv_con_1; + uint32_t spm_dv_sta; + uint32_t conn_xowcn_debug_en; + uint32_t spm_sema_m0; + uint32_t spm_sema_m1; + uint32_t spm_sema_m2; + uint32_t spm_sema_m3; + uint32_t spm_sema_m4; + uint32_t spm_sema_m5; + uint32_t spm_sema_m6; + uint32_t spm_sema_m7; + uint32_t spm2adsp_mailbox; + uint32_t adsp2spm_mailbox; + uint32_t spm_adsp_irq; + uint32_t spm_md32_irq; + uint32_t spm2pmcu_mailbox_0; + uint32_t spm2pmcu_mailbox_1; + uint32_t spm2pmcu_mailbox_2; + uint32_t spm2pmcu_mailbox_3; + uint32_t pmcu2spm_mailbox_0; + uint32_t pmcu2spm_mailbox_1; + uint32_t pmcu2spm_mailbox_2; + uint32_t pmcu2spm_mailbox_3; + uint32_t ufs_psri_sw; + uint32_t ufs_psri_sw_set; + uint32_t ufs_psri_sw_clr; + uint32_t spm_ap_sema; + uint32_t spm_spm_sema; + uint32_t spm_dvfs_con; + uint32_t spm_dvfs_con_sta; + uint32_t spm_pmic_spmi_con; + uint8_t reserved19[4]; + uint32_t spm_dvfs_cmd0; + uint32_t spm_dvfs_cmd1; + uint32_t spm_dvfs_cmd2; + uint32_t spm_dvfs_cmd3; + uint32_t spm_dvfs_cmd4; + uint32_t spm_dvfs_cmd5; + uint32_t spm_dvfs_cmd6; + uint32_t spm_dvfs_cmd7; + uint32_t spm_dvfs_cmd8; + uint32_t spm_dvfs_cmd9; + uint32_t spm_dvfs_cmd10; + uint32_t spm_dvfs_cmd11; + uint32_t spm_dvfs_cmd12; + uint32_t spm_dvfs_cmd13; + uint32_t spm_dvfs_cmd14; + uint32_t spm_dvfs_cmd15; + uint32_t spm_dvfs_cmd16; + uint32_t spm_dvfs_cmd17; + uint32_t spm_dvfs_cmd18; + uint32_t spm_dvfs_cmd19; + uint32_t spm_dvfs_cmd20; + uint32_t spm_dvfs_cmd21; + uint32_t spm_dvfs_cmd22; + uint32_t spm_dvfs_cmd23; + uint32_t sys_timer_value_l; + uint32_t sys_timer_value_h; + uint32_t sys_timer_start_l; + uint32_t sys_timer_start_h; + uint32_t sys_timer_latch_l_00; + uint32_t sys_timer_latch_h_00; + uint32_t sys_timer_latch_l_01; + uint32_t sys_timer_latch_h_01; + uint32_t sys_timer_latch_l_02; + uint32_t sys_timer_latch_h_02; + uint32_t sys_timer_latch_l_03; + uint32_t sys_timer_latch_h_03; + uint32_t sys_timer_latch_l_04; + uint32_t sys_timer_latch_h_04; + uint32_t sys_timer_latch_l_05; + uint32_t sys_timer_latch_h_05; + uint32_t sys_timer_latch_l_06; + uint32_t sys_timer_latch_h_06; + uint32_t sys_timer_latch_l_07; + uint32_t sys_timer_latch_h_07; + uint32_t sys_timer_latch_l_08; + uint32_t sys_timer_latch_h_08; + uint32_t sys_timer_latch_l_09; + uint32_t sys_timer_latch_h_09; + uint32_t sys_timer_latch_l_10; + uint32_t sys_timer_latch_h_10; + uint32_t sys_timer_latch_l_11; + uint32_t sys_timer_latch_h_11; + uint32_t sys_timer_latch_l_12; + uint32_t sys_timer_latch_h_12; + uint32_t sys_timer_latch_l_13; + uint32_t sys_timer_latch_h_13; + uint32_t sys_timer_latch_l_14; + uint32_t sys_timer_latch_h_14; + uint32_t sys_timer_latch_l_15; + uint32_t sys_timer_latch_h_15; + uint32_t pcm_wdt_latch_0; + uint32_t pcm_wdt_latch_1; + uint32_t pcm_wdt_latch_2; + uint32_t pcm_wdt_latch_3; + uint32_t pcm_wdt_latch_4; + uint32_t pcm_wdt_latch_5; + uint32_t pcm_wdt_latch_6; + uint32_t pcm_wdt_latch_7; + uint32_t pcm_wdt_latch_8; + uint32_t pcm_wdt_latch_9; + uint32_t pcm_wdt_latch_10; + uint32_t pcm_wdt_latch_11; + uint32_t pcm_wdt_latch_12; + uint32_t pcm_wdt_latch_13; + uint32_t pcm_wdt_latch_14; + uint32_t pcm_wdt_latch_15; + uint32_t pcm_wdt_latch_16; + uint32_t pcm_wdt_latch_17; + uint32_t pcm_wdt_latch_18; + uint32_t pcm_wdt_latch_spare_0; + uint32_t pcm_wdt_latch_spare_1; + uint32_t pcm_wdt_latch_spare_2; + uint8_t reserved20[24]; + uint32_t pcm_wdt_latch_conn_0; + uint32_t pcm_wdt_latch_conn_1; + uint32_t pcm_wdt_latch_conn_2; + uint8_t reserved21[36]; + uint32_t dramc_gating_err_latch_ch0_0; + uint32_t dramc_gating_err_latch_ch0_1; + uint32_t dramc_gating_err_latch_ch0_2; + uint32_t dramc_gating_err_latch_ch0_3; + uint32_t dramc_gating_err_latch_ch0_4; + uint32_t dramc_gating_err_latch_ch0_5; + uint32_t dramc_gating_err_latch_ch0_6; + uint8_t reserved22[56]; + uint32_t dramc_gating_err_latch_spare_0; + uint8_t reserved23[8]; + uint32_t spm_ack_chk_con_0; + uint32_t spm_ack_chk_pc_0; + uint32_t spm_ack_chk_sel_0; + uint32_t spm_ack_chk_timer_0; + uint32_t spm_ack_chk_sta_0; + uint32_t spm_ack_chk_swint_0; + uint32_t spm_ack_chk_con_1; + uint32_t spm_ack_chk_pc_1; + uint32_t spm_ack_chk_sel_1; + uint32_t spm_ack_chk_timer_1; + uint32_t spm_ack_chk_sta_1; + uint32_t spm_ack_chk_swint_1; + uint32_t spm_ack_chk_con_2; + uint32_t spm_ack_chk_pc_2; + uint32_t spm_ack_chk_sel_2; + uint32_t spm_ack_chk_timer_2; + uint32_t spm_ack_chk_sta_2; + uint32_t spm_ack_chk_swint_2; + uint32_t spm_ack_chk_con_3; + uint32_t spm_ack_chk_pc_3; + uint32_t spm_ack_chk_sel_3; + uint32_t spm_ack_chk_timer_3; + uint32_t spm_ack_chk_sta_3; + uint32_t spm_ack_chk_swint_3; + uint32_t spm_counter_0; + uint32_t spm_counter_1; + uint32_t spm_counter_2; + uint32_t sys_timer_con; + uint32_t spm_twam_con; + uint32_t spm_twam_window_len; + uint32_t spm_twam_idle_sel; + uint32_t spm_twam_event_clear; + uint32_t opp0_table; + uint32_t opp1_table; + uint32_t opp2_table; + uint32_t opp3_table; + uint32_t opp4_table; + uint32_t opp5_table; + uint32_t opp6_table; + uint32_t opp7_table; + uint32_t opp8_table; + uint32_t opp9_table; + uint32_t opp10_table; + uint32_t opp11_table; + uint32_t opp12_table; + uint32_t opp13_table; + uint32_t opp14_table; + uint32_t opp15_table; + uint32_t opp16_table; + uint32_t opp17_table; + uint32_t shu0_array; + uint32_t shu1_array; + uint32_t shu2_array; + uint32_t shu3_array; + uint32_t shu4_array; + uint32_t shu5_array; + uint32_t shu6_array; + uint32_t shu7_array; + uint32_t shu8_array; + uint32_t shu9_array; + uint32_t ssusb_top_pwr_con; + uint32_t ssusb_top_p1_pwr_con; + uint32_t adsp_infra_pwr_con; + uint32_t adsp_ao_pwr_con; +}; + +check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); +check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); +check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); +check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8); +check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +#endif /* SOC_MEDIATEK_MT8186_SPM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2b493e464be9d617226cc8a9875ee3ddb759de Gerrit-Change-Number: 59248 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMA
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59247 ) Change subject: soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMA ...................................................................... soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMA 1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/mcucfg.h M src/soc/mediatek/mt8186/pll.c M src/soc/mediatek/mt8186/soc.c 4 files changed, 15 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/59247/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 7a61bbf..2107ab8 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c @@ -31,6 +32,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c diff --git a/src/soc/mediatek/mt8186/include/soc/mcucfg.h b/src/soc/mediatek/mt8186/include/soc/mcucfg.h index 2418406..48ca33d 100644 --- a/src/soc/mediatek/mt8186/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8186/include/soc/mcucfg.h @@ -942,6 +942,6 @@ check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2_rd, 0x7ff8); check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); -static struct mt8186_mcucfg_regs *const mt8186_mcucfg = (void *)MCUCFG_BASE; +static struct mt8186_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; #endif /* SOC_MEDIATEK_MT8186_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 8201a5a..7f9d748 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -425,13 +425,13 @@ setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL1_EN); setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL2_EN); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603); write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603); @@ -450,7 +450,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN); @@ -463,13 +463,13 @@ udelay(PLL_EN_DELAY); /* switch clock source back to armpll_ll */ - clrsetbits32(&mt8186_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_raise_cci_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN); @@ -482,7 +482,7 @@ udelay(PLL_EN_DELAY); /* switch clock source back to ccipll */ - clrsetbits32(&mt8186_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index 360893c..dcb9703 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Gerrit-Change-Number: 59247 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek: move functions of mmu operation to common folder
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59246 ) Change subject: soc/mediatek: move functions of mmu operation to common folder ...................................................................... soc/mediatek: move functions of mmu operation to common folder Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder which are the same between MT8192, MT8195 and MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d --- R src/soc/mediatek/common/mmu_cmops.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/mcucfg.h D src/soc/mediatek/mt8192/mmu_operations.c M src/soc/mediatek/mt8192/pll.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/mcucfg.h M src/soc/mediatek/mt8195/pll.c 8 files changed, 28 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59246/1 diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/common/mmu_cmops.c similarity index 88% rename from src/soc/mediatek/mt8195/mmu_operations.c rename to src/soc/mediatek/common/mmu_cmops.c index de6e8bc..4b81a27 100644 --- a/src/soc/mediatek/mt8195/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_cmops.c @@ -12,7 +12,7 @@ { unsigned long v; - SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, + SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); dsb(); @@ -25,7 +25,7 @@ __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); } while (((v >> 0x4) & 0xf) != 0xf); - SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, + SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d713e4d..e5ca485 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -30,7 +30,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/memory.c ../common/memory_test.c -romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c @@ -55,7 +55,7 @@ ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c mmu_operations.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c diff --git a/src/soc/mediatek/mt8192/include/soc/mcucfg.h b/src/soc/mediatek/mt8192/include/soc/mcucfg.h index 1d270ec..b9f1f38 100644 --- a/src/soc/mediatek/mt8192/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8192/include/soc/mcucfg.h @@ -1033,6 +1033,6 @@ check_member(mt8192_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); check_member(mt8192_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); -static struct mt8192_mcucfg_regs *const mt8192_mcucfg = (void *)MCUCFG_BASE; +static struct mt8192_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; #endif /* SOC_MEDIATEK_MT8192_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c deleted file mode 100644 index e3bc622..0000000 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <soc/mcucfg.h> -#include <soc/mmu_operations.h> -#include <soc/symbols.h> - -DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) -DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) - -void mtk_soc_disable_l2c_sram(void) -{ - unsigned long v; - - SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, - MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); - dsb(); - - __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); - v |= (0xf << 4); - __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); - dsb(); - - do { - __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); - } while (((v >> 0x4) & 0xf) != 0xf); - - SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, - MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); - dsb(); -} - -/* mtk_soc_after_dram is called in romstage */ -void mtk_soc_after_dram(void) -{ - mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), - NONSECURE_UNCACHED_MEM); -} diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index e49e222..c9e2753 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -417,13 +417,13 @@ } /* MCUCFG CLKMUX */ - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); @@ -481,7 +481,7 @@ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); /* switch ca55 clock source to intermediate clock */ - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); @@ -494,7 +494,7 @@ udelay(PLL_EN_DELAY); /* switch ca55 clock source back to armpll_ll */ - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); @@ -566,7 +566,7 @@ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); /* switch cci clock source to intermediate clock */ - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); @@ -579,7 +579,7 @@ udelay(PLL_EN_DELAY); /* switch cci clock source back to ccipll */ - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index c362899..39ccb16 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -34,7 +34,7 @@ romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/memory.c romstage-y += ../common/memory_test.c -romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/pll.c pll.c romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -64,7 +64,7 @@ ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c mmu_operations.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c diff --git a/src/soc/mediatek/mt8195/include/soc/mcucfg.h b/src/soc/mediatek/mt8195/include/soc/mcucfg.h index bb39096..3e99e00 100644 --- a/src/soc/mediatek/mt8195/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8195/include/soc/mcucfg.h @@ -964,6 +964,6 @@ check_member(mt8195_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0); check_member(mt8195_mcucfg_regs, bus_plldiv_cfg, 0x22e0); -static struct mt8195_mcucfg_regs *const mt8195_mcucfg = (void *)MCUCFG_BASE; +static struct mt8195_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; #endif /* SOC_MEDIATEK_MT8195_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 8fd424d..df4ae30 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -707,13 +707,13 @@ } /* MCUCFG CLKMUX */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* enable infrasys DCM */ setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21); @@ -765,7 +765,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN); @@ -778,13 +778,13 @@ udelay(PLL_EN_DELAY); /* switch clock source back to armpll_ll */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_raise_cci_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN); @@ -797,7 +797,7 @@ udelay(PLL_EN_DELAY); /* switch clock source back to ccipll */ - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_set_tvd_pll1_freq(u32 freq) -- To view, visit https://review.coreboot.org/c/coreboot/+/59246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d Gerrit-Change-Number: 59246 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8186: Add support for PMIC MT6366
by Rex-BC Chen (Code Review) 12 Nov '21

12 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59245 ) Change subject: soc/mediatek/mt8186: Add support for PMIC MT6366 ...................................................................... soc/mediatek/mt8186: Add support for PMIC MT6366 Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo(a)mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 --- M src/mainboard/google/corsola/romstage.c M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/addressmap.h A src/soc/mediatek/mt8186/include/soc/mt6366.h A src/soc/mediatek/mt8186/include/soc/pmic_wrap.h A src/soc/mediatek/mt8186/mt6366.c A src/soc/mediatek/mt8186/pmic_wrap.c 9 files changed, 1,554 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/59245/1 diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index 891dc1b..07b9127 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/mt6366.h> void platform_romstage_main(void) { + mt6366_init(); } diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 61efaec..afd00d5 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -81,8 +81,13 @@ RDATA_WACS_FSM_SHIFT = 16, RDATA_WACS_REQ_SHIFT = 19, RDATA_SYNC_IDLE_SHIFT, - RDATA_INIT_DONE_SHIFT, - RDATA_SYS_IDLE_SHIFT, + RDATA_INIT_DONE_V1_SHIFT, + RDATA_SYS_IDLE_V1_SHIFT, +}; + +enum { + RDATA_INIT_DONE_V2_SHIFT = 22, /* 8186 */ + RDATA_SYS_IDLE_V2_SHIFT = 23, /* 8186 */ }; enum { diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 4e044a1..d732994 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -103,12 +103,17 @@ u32 wacs_addr = 0; u32 wacs_cmd = 0; u32 wait_result = 0; + u32 shift; if (init_check) { reg_rdata = read32(&mtk_pwrap->wacs2_rdata); /* Prevent someone to use pwrap before pwrap init */ - if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & - RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + if (CONFIG(SOC_MEDIATEK_MT8186)) + shift = RDATA_INIT_DONE_V2_SHIFT; + else + shift = RDATA_INIT_DONE_V1_SHIFT; + + if (((reg_rdata >> shift) & RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { pwrap_err("Pwrap initialization isn't finished\n"); return E_PWR_NOT_INIT_DONE; } diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index cb07ac0..7a61bbf 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c +romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c @@ -35,6 +36,7 @@ ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/wdt.c wdt.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index 20a48ad..28ba369 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -27,6 +27,7 @@ GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000, DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000, SYSTIMER_BASE = IO_PHYS + 0x00017000, diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h new file mode 100644 index 0000000..ef711c9 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef __SOC_MEDIATEK_MT6366_H__ +#define __SOC_MEDIATEK_MT6366_H__ + +#include <types.h> + +enum { + PMIC_SWCID = 0x000a, + PMIC_VM_MODE = 0x004e, + PMIC_TOP_CKPDN_CON0_SET = 0x010e, + PMIC_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_TOP_CKHWEN_CON0_SET = 0x012c, + PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, + PMIC_TOP_RST_MISC = 0x014c, + PMIC_TOP_RST_MISC_SET = 0x014e, + PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, + PMIC_TOP_TMA_KEY = 0x03a8, + PMIC_PWRHOLD = 0x0a08, + PMIC_CPSDSA4 = 0x0a2e, + PMIC_VCORE_OP_EN = 0x1490, + PMIC_VCORE_DBG0 = 0x149e, + PMIC_VCORE_VOSEL = 0x14aa, + PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_VDRAM1_OP_EN = 0x1610, + PMIC_VDRAM1_DBG0 = 0x161e, + PMIC_VDRAM1_VOSEL = 0x1626, + PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VDDQ_OP_EN = 0x1b16, + PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VDDQ_ELR_0 = 0x1ec4, +}; + +enum mt6366_regulator_id { + MT6366_VCORE = 0, + MT6366_VDRAM1, + MT6366_VDDQ, + MT6366_REGULATOR_NUM, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +void mt6366_init(void); +void mt6366_set_power_hold(bool enable); +void mt6366_set_vsim2_cali_mv(u32 vsim2_mv); +void mt6366_init_scp_voltage(void); +void mt6366_set_voltage(enum mt6366_regulator_id id, u32 vcore_uv); +u32 mt6366_get_voltage(enum mt6366_regulator_id id); + +#endif /* __SOC_MEDIATEK_MT6366_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h new file mode 100644 index 0000000..65710a1 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef __SOC_MEDIATEK_MT8186_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8186_PMIC_WRAP_H__ + +#include <soc/addressmap.h> +#include <soc/pmic_wrap_common.h> +#include <types.h> + +struct mt8186_pwrap_regs { + u32 mux_sel; + u32 wrap_en; + u32 dio_en; + u32 si_sample_ctrl; + u32 si_sample_ctrl_1; + u32 si_sample_ctrl_2; + u32 si_sample_ctrl_3; + u32 si_sample_ctrl_ulposc; + u32 rddmy; + u32 cshext_write; + u32 cshext_read; + u32 cslext_write; + u32 cslext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 staupd_ctrl; + u32 staupd_grpen; + u32 eint_sta0_adr; + u32 eint_sta1_adr; + u32 eint_sta; + u32 eint_clr; + u32 eint_ctrl; + u32 staupd_man_trig; + u32 staupd_sta; + u32 wrap_sta; + u32 harb_init; + u32 harb_hprio; + u32 hiprio_arb_en; + u32 harb_sta0; + u32 harb_sta1; + u32 harb_sta2; + u32 man_en; + u32 man_cmd; + u32 man_rdata; + u32 man_vldclr; + u32 wacs0_en; + u32 init_done0; + u32 wacs1_en; + u32 init_done1; + u32 wacs2_en; + u32 init_done2; + u32 wacs3_en; + u32 init_done3; + u32 wacs_p2p_en; + u32 init_done_p2p; + u32 wacs_md32_en; + u32 init_done_md32; + u32 int0_en; + u32 int0_flg_raw; + u32 int0_flg; + u32 int0_clr; + u32 int1_en; + u32 int1_flg_raw; + u32 int1_flg; + u32 int1_clr; + u32 sig_adr; + u32 sig_mode; + u32 sig_value; + u32 sig_errval; + u32 crc_en; + u32 timer_ctrl; + u32 timer_sta; + u32 wdt_ctrl; + u32 wdt_src_en_0; + u32 wdt_src_en_1; + u32 wdt_flg_0; + u32 wdt_flg_1; + u32 debug_int_sel; + u32 dvfs_adr0; + u32 dvfs_wdata0; + u32 dvfs_adr1; + u32 dvfs_wdata1; + u32 dvfs_adr2; + u32 dvfs_wdata2; + u32 dvfs_adr3; + u32 dvfs_wdata3; + u32 dvfs_adr4; + u32 dvfs_wdata4; + u32 dvfs_adr5; + u32 dvfs_wdata5; + u32 dvfs_adr6; + u32 dvfs_wdata6; + u32 dvfs_adr7; + u32 dvfs_wdata7; + u32 dvfs_adr8; + u32 dvfs_wdata8; + u32 dvfs_adr9; + u32 dvfs_wdata9; + u32 dvfs_adr10; + u32 dvfs_wdata10; + u32 dvfs_adr11; + u32 dvfs_wdata11; + u32 dvfs_adr12; + u32 dvfs_wdata12; + u32 dvfs_adr13; + u32 dvfs_wdata13; + u32 dvfs_adr14; + u32 dvfs_wdata14; + u32 dvfs_adr15; + u32 dvfs_wdata15; + u32 dcxo_enable; + u32 dcxo_conn_adr0; + u32 dcxo_conn_wdata0; + u32 dcxo_conn_adr1; + u32 dcxo_conn_wdata1; + u32 dcxo_nfc_adr0; + u32 dcxo_nfc_wdata0; + u32 dcxo_nfc_adr1; + u32 dcxo_nfc_wdata1; + u32 spminf_sta_0; + u32 spminf_sta_1; + u32 spminf_backup_sta; + u32 scpinf_sta; + u32 srclken_rcinf_sta_0; + u32 srclken_rcinf_sta_1; + u32 mcu_pminf_sta_0; + u32 mcu_pminf_sta_1; + u32 cipher_key_sel; + u32 cipher_iv_sel; + u32 cipher_en; + u32 cipher_rdy; + u32 cipher_mode; + u32 cipher_swrst; + u32 dcm_en; + u32 dcm_dbc_prd; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 ext_gps_auxadc_rdata_addr; + u32 gpsinf_0_sta; + u32 gpsinf_1_sta; + u32 md_adcinf_ctrl; + u32 md_auxadc_rdata_latest_addr; + u32 md_auxadc_rdata_wp_addr; + u32 md_auxadc_rdata[32]; + u32 md_adcinf_0_sta_0; + u32 md_adcinf_0_sta_1; + u32 md_adcinf_1_sta_0; + u32 md_adcinf_1_sta_1; + u32 swrst; + u32 sleep_protection_ctrl; + u32 spm_sleep_gating_ctrl; + u32 scp_sleep_gating_ctrl; + u32 busy_sta; + u32 busy_sta_latched_wdt; + u32 priority_user_sel_0; + u32 priority_user_sel_1; + u32 priority_user_sel_2; + u32 priority_user_sel_3; + u32 priority_user_sel_4; + u32 arbiter_out_sel_0; + u32 arbiter_out_sel_1; + u32 arbiter_out_sel_2; + u32 arbiter_out_sel_3; + u32 arbiter_out_sel_4; + u32 starv_counter_0; + u32 starv_counter_1; + u32 starv_counter_2; + u32 starv_counter_3; + u32 starv_counter_4; + u32 starv_counter_5; + u32 starv_counter_6; + u32 starv_counter_7; + u32 starv_counter_8; + u32 starv_counter_9; + u32 starv_counter_10; + u32 starv_counter_11; + u32 starv_counter_12; + u32 starv_counter_13; + u32 starv_counter_14; + u32 starv_counter_15; + u32 starv_counter_16; + u32 starv_int_en; + u32 starv_counter_0_status; + u32 starv_counter_1_status; + u32 starv_counter_2_status; + u32 starv_counter_3_status; + u32 starv_counter_4_status; + u32 starv_counter_5_status; + u32 starv_counter_6_status; + u32 starv_counter_7_status; + u32 starv_counter_8_status; + u32 starv_counter_9_status; + u32 starv_counter_10_status; + u32 starv_counter_11_status; + u32 starv_counter_12_status; + u32 starv_counter_13_status; + u32 starv_counter_14_status; + u32 starv_counter_15_status; + u32 starv_counter_16_status; + u32 starv_counter_clr; + u32 starv_prio_status; + u32 monitor_ctrl; + u32 monitor_target_channel_0; + u32 monitor_target_channel_1; + u32 monitor_target_channel_2; + u32 monitor_target_channel_3; + u32 monitor_target_channel_4; + u32 monitor_target_channel_5; + u32 monitor_target_channel_6; + u32 monitor_target_channel_7; + u32 monitor_target_write; + u32 monitor_target_adr_0; + u32 monitor_target_adr_1; + u32 monitor_target_adr_2; + u32 monitor_target_adr_3; + u32 monitor_target_adr_4; + u32 monitor_target_adr_5; + u32 monitor_target_adr_6; + u32 monitor_target_adr_7; + u32 monitor_target_wdata_0; + u32 monitor_target_wdata_1; + u32 monitor_target_wdata_2; + u32 monitor_target_wdata_3; + u32 monitor_target_wdata_4; + u32 monitor_target_wdata_5; + u32 monitor_target_wdata_6; + u32 monitor_target_wdata_7; + u32 channel_sequence_0; + u32 channel_sequence_1; + u32 channel_sequence_2; + u32 channel_sequence_3; + u32 channel_sequence_4; + u32 channel_sequence_5; + u32 channel_sequence_6; + u32 channel_sequence_7; + u32 write_sequence; + u32 adr_sequence_0; + u32 adr_sequence_1; + u32 adr_sequence_2; + u32 adr_sequence_3; + u32 adr_sequence_4; + u32 adr_sequence_5; + u32 adr_sequence_6; + u32 adr_sequence_7; + u32 adr_sequence_8; + u32 adr_sequence_9; + u32 adr_sequence_10; + u32 adr_sequence_11; + u32 adr_sequence_12; + u32 adr_sequence_13; + u32 adr_sequence_14; + u32 adr_sequence_15; + u32 wdata_sequence_0; + u32 wdata_sequence_1; + u32 wdata_sequence_2; + u32 wdata_sequence_3; + u32 wdata_sequence_4; + u32 wdata_sequence_5; + u32 wdata_sequence_6; + u32 wdata_sequence_7; + u32 wdata_sequence_8; + u32 wdata_sequence_9; + u32 wdata_sequence_10; + u32 wdata_sequence_11; + u32 wdata_sequence_12; + u32 wdata_sequence_13; + u32 wdata_sequence_14; + u32 wdata_sequence_15; + u32 bwc_options; + u32 reserved1[477]; + u32 wacs0_cmd; + u32 wacs0_rdata; + u32 wacs0_vldclr; + u32 reserved2; + u32 wacs1_cmd; + u32 wacs1_rdata; + u32 wacs1_vldclr; + u32 reserved3; + u32 wacs2_cmd; + u32 wacs2_rdata; + u32 wacs2_vldclr; + u32 reserved4; + u32 wacs3_cmd; + u32 wacs3_rdata; + u32 wacs3_vldclr; +}; + +check_member(mt8186_pwrap_regs, bwc_options, 0x488); +check_member(mt8186_pwrap_regs, wacs3_vldclr, 0xC38); + +static struct mt8186_pwrap_regs * const mtk_pwrap = (void *)PWRAP_BASE; + +enum { + WACS2 = 1 << 2 +}; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0030, + PMIC_DRV_CON1 = PMIC_BASE + 0x0038, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0040, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_RG_SPI_RECORD0 = PMIC_BASE + 0x040A, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040C, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040E, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0426, + PMIC_CPU_INT_STA = PMIC_BASE + 0x042E, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0432, + PMIC_RG_SPI_CON3 = PMIC_BASE + 0x0434, + PMIC_RG_SPI_CON4 = PMIC_BASE + 0x0436, + PMIC_RG_SPI_CON5 = PMIC_BASE + 0x0438, + PMIC_RG_SPI_CON6 = PMIC_BASE + 0x043A, + PMIC_RG_SPI_CON7 = PMIC_BASE + 0x043C, + PMIC_RG_SPI_CON8 = PMIC_BASE + 0x043E, + PMIC_RG_SPI_CON13 = PMIC_BASE + 0x0448, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044A, + PMIC_PPCCTL0 = PMIC_BASE + 0x0A08, + PMIC_AUXADC_ADC17 = PMIC_BASE + 0x10AA, + PMIC_AUXADC_ADC31 = PMIC_BASE + 0x10C6, + PMIC_AUXADC_ADC32 = PMIC_BASE + 0x10C8, + PMIC_AUXADC_ADC35 = PMIC_BASE + 0x10CE, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, + PMIC_AUXADC_RQST1 = PMIC_BASE + 0x110A, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING, +}; + +enum { + GPS_MAIN = 0x40, + GPS_SUBSYS = 0x80, +}; + +enum { + SIG_PMIC_0 = 0x1 << 0, + INT_STA_PMIC_0 = 0x1 << 2, + MD_ADC_DATA0 = 0x1 << 4, + MD_ADC_DATA1 = 0x1 << 5, + GPS_ADC_DATA0 = 0x1 << 6, + GPS_ADC_DATA1 = 0x1 << 7, +}; + +enum { + MD = 1, + MD_DVFS = 2, + POWER_HW = 4, + POWER_HW_BACKUP = 8, + ARB_PRIORITY = MD | MD_DVFS | POWER_HW | POWER_HW_BACKUP, +}; + +enum { + ARB_WACS0 = 0x1, + ARB_WACS2 = 0x1 << 2, + ARB_WACS_P2P = 0x1 << 4, + ARB_WACS_MD32 = 0x1 << 5, + ARB_MD = 0x1 << 6, + ARB_WACS_POWER_HW = 0x1 << 9, + ARB_DCXO_CONN = 0x1 << 11, + ARB_DCXO_NFC = 0x1 << 12, + ARB_MD_ADC0 = 0x1 << 13, + ARB_MD_ADC1 = 0x1 << 14, + ARB_GPS_0 = 0x1 << 15, + ARB_GPS_1 = 0x1 << 16, + STAUPD_HARB = 0x1 << 17, + ARB_USER_EN = ARB_WACS0 | ARB_WACS2 | ARB_WACS_P2P | ARB_WACS_MD32 | + ARB_MD | ARB_WACS_POWER_HW | ARB_DCXO_CONN | ARB_DCXO_NFC | + ARB_MD_ADC0 | ARB_MD_ADC1 | ARB_GPS_0 | ARB_GPS_1 | STAUPD_HARB, +}; + +enum { + STA_PD_98_5_US = 0x5, +}; + +enum { + WATCHDOG_TIMER_7_5_MS = 0xF, +}; + +enum { + WDT_MONITOR_ALL = 0xFFFF, +}; + +enum { + MONITOR_LATCH_MATCHED_TRANS = 0x1 << 28, + STARV_15 = 0x1 << 24, + DCXO = 0x1 << 19, + MONITOR_ALL_INT = 0xFFFFFFFF, + INT0_MONITOR = MONITOR_ALL_INT, + INT1_MONITOR = MONITOR_ALL_INT & + ~MONITOR_LATCH_MATCHED_TRANS & ~STARV_15 & ~DCXO, +}; + +enum { + SPI_CLK = 0x1, + SPI_CSN = 0x1 << 1, + SPI_MOSI = 0x1 << 2, + SPI_MISO = 0x1 << 3, + SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, + SPI_SMT = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO), + SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, +}; + +enum { + IO_4_MA = 0x8, +}; + +enum { + SPI_CLK_SHIFT = 0, + SPI_CSN_SHIFT = 4, + SPI_MOSI_SHIFT = 8, + SPI_MISO_SHIFT = 12, + SPI_DRIVING = (IO_4_MA << SPI_CLK_SHIFT | IO_4_MA << SPI_CSN_SHIFT | + IO_4_MA << SPI_MOSI_SHIFT | IO_4_MA << SPI_MISO_SHIFT), +}; + +enum { + DUMMY_READ_CYCLES = 0x8, +}; +#endif /* __SOC_MEDIATEK_MT8186_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c new file mode 100644 index 0000000..40d31e5 --- /dev/null +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -0,0 +1,709 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6366.h> +#include <soc/pmic_wrap.h> +#include <soc/regulator.h> +#include <timer.h> + +static struct pmic_setting init_setting[] = { + {0x1E, 0xA, 0xA, 0}, + {0x22, 0x1F00, 0x1F00, 0}, + {0x2E, 0x1, 0x1, 0}, + {0x30, 0x1, 0x1, 0}, + {0x36, 0x8888, 0xFFFF, 0}, + {0x3A, 0x8888, 0xFFFF, 0}, + {0x3C, 0x8888, 0xFFFF, 0}, + {0x3E, 0x888, 0xFFF, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x18, 0x18, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x12A, 0x100, 0x180, 0}, + {0x134, 0x80, 0x2890, 0}, + {0x14C, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x790, 0x280, 0x780, 0}, + {0x7AC, 0x0, 0x2000, 0}, + {0x98A, 0x1840, 0x1E40, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA24, 0x1E00, 0x1F00, 0}, + {0xA38, 0x0, 0x100, 0}, + {0xA3C, 0x81E0, 0x81E0, 0}, + {0xA44, 0xFFFF, 0xFFFF, 0}, + {0xA46, 0xFC00, 0xFC00, 0}, + {0xC8A, 0x4, 0xC, 0}, + {0xF8C, 0xAAA, 0xAAA, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11A2, 0x0, 0x3000, 0}, + {0x11B0, 0x4000, 0x4000, 0}, + {0x11B4, 0x0, 0x100, 0}, + {0x123A, 0x8040, 0x83FF, 0}, + {0x123E, 0x4, 0x4, 0}, + {0x1242, 0x1, 0x1, 0}, + {0x1260, 0x0, 0x154, 0}, + {0x1312, 0x8, 0x8, 0}, + {0x1334, 0x0, 0x100, 0}, + {0x138A, 0x10, 0x7F, 0}, + {0x138C, 0x15, 0x7F, 0}, + {0x138E, 0x1030, 0x3030, 0}, + {0x140A, 0x10, 0x7F, 0}, + {0x140C, 0x15, 0x7F, 0}, + {0x140E, 0x1030, 0x3030, 0}, + {0x148A, 0x10, 0x7F, 0}, + {0x148E, 0x1030, 0x3030, 0}, + {0x14A2, 0x20, 0x20, 0}, + {0x150A, 0x10, 0x7F, 0}, + {0x150E, 0x1030, 0x3030, 0}, + {0x158A, 0x8, 0x7F, 0}, + {0x158C, 0x90C, 0x7F7F, 0}, + {0x158E, 0x1030, 0x3030, 0}, + {0x159C, 0x8, 0xC, 0}, + {0x15A2, 0x20, 0x20, 0}, + {0x168A, 0x50, 0x7F, 0}, + {0x168C, 0x1964, 0x7F7F, 0}, + {0x168E, 0x2020, 0x3030, 0}, + {0x16A2, 0x20, 0x20, 0}, + {0x16AA, 0x50, 0x7F, 0}, + {0x170C, 0x1964, 0x7F7F, 0}, + {0x170E, 0x2020, 0x3030, 0}, + {0x172A, 0x44, 0x7F, 0}, + {0x178C, 0x202, 0x7F7F, 0}, + {0x178E, 0x70, 0x73, 0}, + {0x1790, 0xC, 0xC, 0}, + {0x1798, 0x2810, 0x3F3F, 0}, + {0x179A, 0x800, 0x3F00, 0}, + {0x179E, 0x1, 0x1, 0}, + {0x1808, 0x2000, 0x3000, 0}, + {0x180C, 0x60, 0x60, 0}, + {0x1814, 0x3FF0, 0x7FFF, 0}, + {0x1816, 0x3, 0x7, 0}, + {0x181A, 0x6081, 0xFFBF, 0}, + {0x181C, 0x503, 0x787, 0}, + {0x181E, 0xA462, 0xFFFF, 0}, + {0x1820, 0xA662, 0xFFFF, 0}, + {0x1824, 0xDB6, 0xFFF, 0}, + {0x1828, 0x160, 0x160, 0}, + {0x1830, 0x3FF0, 0x7FFF, 0}, + {0x1832, 0x3, 0x7, 0}, + {0x1836, 0x6081, 0xFFBF, 0}, + {0x1838, 0x503, 0x787, 0}, + {0x183A, 0xA262, 0xFFFF, 0}, + {0x183C, 0xA262, 0xFFFF, 0}, + {0x1840, 0xDB6, 0xFFF, 0}, + {0x1888, 0x420, 0xE7C, 0}, + {0x188A, 0x801, 0x3C07, 0}, + {0x188C, 0x1F, 0x3F, 0}, + {0x188E, 0x129A, 0xFFFF, 0}, + {0x1894, 0x58, 0x1F8, 0}, + {0x1896, 0x1C, 0x7C, 0}, + {0x1898, 0x1805, 0x3C07, 0}, + {0x189A, 0xF, 0xF, 0}, + {0x189C, 0x221A, 0xFFFF, 0}, + {0x18A0, 0x2E, 0x3F, 0}, + {0x18A2, 0x0, 0x40, 0}, + {0x18A4, 0x2C06, 0x3C07, 0}, + {0x18A6, 0xF, 0xF, 0}, + {0x18A8, 0x221A, 0xFFFF, 0}, + {0x18AC, 0x2E, 0x3F, 0}, + {0x18AE, 0x0, 0x40, 0}, + {0x18B0, 0x1805, 0x3C07, 0}, + {0x18B2, 0xF, 0xF, 0}, + {0x18B4, 0x221A, 0xFFFF, 0}, + {0x18B8, 0x2E, 0x3F, 0}, + {0x18BC, 0x50, 0x4F0, 0}, + {0x18BE, 0x3C, 0xFC, 0}, + {0x18C0, 0x0, 0x300, 0}, + {0x18C2, 0x8886, 0xFFFF, 0}, + {0x1A0E, 0x3, 0x3, 0}, + {0x1A10, 0x1, 0x1, 0}, + {0x1A12, 0x0, 0x1, 0}, + {0x1A14, 0x0, 0x1, 0}, + {0x1A16, 0x0, 0x1, 0}, + {0x1A18, 0x0, 0x1, 0}, + {0x1A1A, 0x0, 0x1, 0}, + {0x1A1C, 0x0, 0x1, 0}, + {0x1A1E, 0x0, 0x1, 0}, + {0x1A20, 0x0, 0x1, 0}, + {0x1A22, 0x0, 0x1, 0}, + {0x1A24, 0x0, 0x1, 0}, + {0x1A26, 0x0, 0x1, 0}, + {0x1A2C, 0x0, 0x1, 0}, + {0x1A2E, 0x0, 0x1, 0}, + {0x1A30, 0x0, 0x1, 0}, + {0x1A32, 0x0, 0x1, 0}, + {0x1A34, 0x0, 0x1, 0}, + {0x1A36, 0x0, 0x1, 0}, + {0x1A38, 0x0, 0x1, 0}, + {0x1A3A, 0x0, 0x1, 0}, + {0x1A3C, 0x0, 0x1, 0}, + {0x1A3E, 0x0, 0x1, 0}, + {0x1A40, 0x0, 0x1, 0}, + {0x1A42, 0x0, 0x1, 0}, + {0x1A44, 0x0, 0x1, 0}, + {0x1A46, 0x0, 0x1, 0}, + {0x1A48, 0x0, 0x1, 0}, + {0x1A4A, 0x0, 0x1, 0}, + {0x1A4C, 0x0, 0x1, 0}, + {0x1A4E, 0x0, 0x1, 0}, + {0x1A50, 0xE7FF, 0xE7FF, 0}, + {0x1A56, 0x7FFF, 0x7FFF, 0}, + {0x1B48, 0x10, 0x7F, 0}, + {0x1B4A, 0xF15, 0x7F7F, 0}, + {0x1B8A, 0x10, 0x7F, 0}, + {0x1B8C, 0xF15, 0x7F7F, 0}, + {0x1BA8, 0x10, 0x7F, 0}, + {0x1BAA, 0xF15, 0x7F7F, 0}, + {0x1BAC, 0x0, 0x3, 0}, + {0x1BCA, 0x10, 0x7F, 0}, + {0x1BCC, 0x70F, 0x7F7F, 0}, + {0x1C9E, 0x38, 0x7F, 0}, + {0x1CA0, 0x70F, 0x7F7F, 0}, + {0x1EA2, 0x1B, 0x1F, 0}, + {0x1EA4, 0xC00, 0x1C00, 0}, + {0x1EA6, 0xC00, 0x1C00, 0}, + {0x1EA8, 0xC00, 0x1C00, 0}, +};; + +static struct pmic_setting lp_setting[] = { + /* Suspend */ + /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ + {0x1390, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ + {0x1490, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ + {0x1510, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ + {0x1590, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ + {0x1690, 0x1, 0x1, 0}, + /* [1:1]: RG_BUCK_VS2_HW0_OP_EN */ + {0x1710, 0x1, 0x1, 1}, + /* [1:1]: RG_BUCK_VS2_HW0_OP_CFG */ + {0x1716, 0x1, 0x1, 1}, + /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_EN */ + {0x1610, 0x1, 0x1, 1}, + /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_CFG */ + {0x1616, 0x1, 0x1, 1}, + /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ + {0x1410, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ + {0x1BD0, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_EN */ + {0x1BAE, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_CFG */ + {0x1BB4, 0x1, 0x1, 1}, + /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ + {0x1B4E, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VXO22_HW0_OP_EN */ + {0x1A8A, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VXO22_HW0_OP_CFG */ + {0x1A90, 0x1, 0x1, 1}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ + {0x1C1E, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ + {0x1C24, 0x0, 0x1, 2}, + /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ + {0x1C32, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ + {0x1C38, 0x0, 0x1, 2}, + /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ + {0x1C46, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ + {0x1D8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ + {0x1C5A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ + {0x1C6E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ + {0x1C9E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ + {0x1C8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ + {0x1B90, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ + {0x1CB2, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VA12_HW0_OP_EN */ + {0x1A9E, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VA12_HW0_OP_CFG */ + {0x1AA4, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUX18_HW0_OP_EN */ + {0x1AB2, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUX18_HW0_OP_CFG */ + {0x1AB8, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUD28_HW0_OP_EN */ + {0x1AC6, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUD28_HW0_OP_CFG */ + {0x1ACC, 0x1, 0x1, 1}, + /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ + {0x1ADA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ + {0x1AEE, 0x1, 0x1, 0}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ + {0x1C0A, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ + {0x1C10, 0x0, 0x1, 2}, + /* [1:1]: RG_LDO_VDRAM2_HW0_OP_EN */ + {0x1B0A, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VDRAM2_HW0_OP_CFG */ + {0x1B10, 0x1, 0x1, 1}, + /* [0:0]: RG_LDO_VMC_SW_OP_EN */ + {0x1CC6, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ + {0x1CDA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ + {0x1B1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ + {0x1D4A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ + {0x1D5E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ + {0x1D0A, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ + {0x1B32, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ + {0x1B38, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ + {0x1B32, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ + {0x1B38, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VBIF28_HW0_OP_EN */ + {0x1DA0, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VBIF28_HW0_OP_CFG */ + {0x1DA6, 0x0, 0x1, 1}, + + /* Deep idle setting */ + /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ + {0x1390, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ + {0x1490, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ + {0x1510, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ + {0x1590, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ + {0x1690, 0x1, 0x1, 0}, + /* [3:3]: RG_BUCK_VS2_HW2_OP_EN */ + {0x1710, 0x1, 0x1, 3}, + /* [3:3]: RG_BUCK_VS2_HW2_OP_CFG */ + {0x1716, 0x1, 0x1, 3}, + /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_EN */ + {0x1610, 0x1, 0x1, 3}, + /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_CFG */ + {0x1616, 0x1, 0x1, 3}, + /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ + {0x1410, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ + {0x1BD0, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_EN */ + {0x1BAE, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_CFG */ + {0x1BB4, 0x1, 0x1, 3}, + /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ + {0x1B4E, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VXO22_HW2_OP_EN */ + {0x1A8A, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VXO22_HW2_OP_CFG */ + {0x1A90, 0x1, 0x1, 3}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ + {0x1C1E, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ + {0x1C24, 0x0, 0x1, 2}, + /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ + {0x1C32, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ + {0x1C38, 0x0, 0x1, 2}, + /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ + {0x1C46, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ + {0x1D8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ + {0x1C5A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ + {0x1C6E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ + {0x1C9E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ + {0x1C8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ + {0x1B90, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ + {0x1CB2, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VA12_HW2_OP_EN */ + {0x1A9E, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VA12_HW2_OP_CFG */ + {0x1AA4, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VAUX18_HW2_OP_EN */ + {0x1AB2, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VAUX18_HW2_OP_CFG */ + {0x1AB8, 0x1, 0x1, 3}, + /* [0:0]: RG_LDO_VAUD28_SW_OP_EN */ + {0x1AC6, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ + {0x1ADA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ + {0x1AEE, 0x1, 0x1, 0}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ + {0x1C0A, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ + {0x1C10, 0x0, 0x1, 2}, + /* [3:3]: RG_LDO_VDRAM2_HW2_OP_EN */ + {0x1B0A, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VDRAM2_HW2_OP_CFG */ + {0x1B10, 0x1, 0x1, 3}, + /* [0:0]: RG_LDO_VMC_SW_OP_EN */ + {0x1CC6, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ + {0x1CDA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ + {0x1B1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ + {0x1D4A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ + {0x1D5E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ + {0x1D0A, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ + {0x1B32, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ + {0x1B38, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ + {0x1B32, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ + {0x1B38, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VBIF28_HW2_OP_EN */ + {0x1DA0, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VBIF28_HW2_OP_CFG */ + {0x1DA6, 0x0, 0x1, 3}, +}; + +static struct pmic_setting scp_setting[] = { + /* scp voltage initialization */ + /* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */ + {0x14A6, 0x20, 0x7F, 0}, + /* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */ + {0x14A6, 0x20, 0x7F, 8}, + /* [0:0]: RG_BUCK_VCORE_SSHUB_EN */ + {0x14A4, 0x1, 0x1, 0}, + /* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */ + {0x14A4, 0x0, 0x1, 1}, + /* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */ + {0x1BC6, 0x40, 0x7F, 0}, + /* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */ + {0x1BC6, 0x40, 0x7F, 8}, + /* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */ + {0x1BC4, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */ + {0x1BC4, 0x0, 0x1, 1}, + /* [4:4]: RG_SRCVOLTEN_LP_EN */ + {0x134, 0x1, 0x1, 4}, +}; + +static const int vddq_votrim[] = { + 0, -10000, -20000, -30000, -40000, -50000, -60000, -70000, + 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, +}; + +static u32 pmic_read_efuse(int i) +{ + u32 efuse_data = 0; + + /* 1. Enable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); + + /* 2. */ + pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); + + /* 3. Set row to read */ + pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); + + /* 4. Toggle RG_OTP_RD_TRIG */ + if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) + pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); + else + pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); + + /* 5. Polling RG_OTP_RD_BUSY = 0 */ + udelay(300); + while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) + ; + + /* 6. Read RG_OTP_DOUT_SW */ + udelay(100); + efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + + /* 7. Disable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); + + return efuse_data; +} + +static int pmic_get_efuse_votrim(void) +{ + const u32 cali_efuse = pmic_read_efuse(106) & 0xF; + assert(cali_efuse < ARRAY_SIZE(vddq_votrim)); + return vddq_votrim[cali_efuse]; +} + +static u32 pmic_get_vcore_vol(void) +{ + u32 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vcore_vol(u32 vcore_uv) +{ + u32 vol_reg; + + assert(vcore_uv >= 500000); + assert(vcore_uv <= 1100000); + + vol_reg = (vcore_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vdram1_vol(void) +{ + u32 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); + return 500000 + vol_reg * 12500; +} + +static void pmic_set_vdram1_vol(u32 vdram_uv) +{ + u32 vol_reg; + + assert(vdram_uv >= 500000); + assert(vdram_uv <= 1300000); + + vol_reg = (vdram_uv - 500000) / 12500; + + pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vddq_vol(void) +{ + int efuse_votrim; + u32 cali_trim; + + if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) + return 0; + + efuse_votrim = pmic_get_efuse_votrim(); + cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); + return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; +} + +static void pmic_set_vddq_vol(u32 vddq_uv) +{ + int target_mv, dram2_ori_mv, cali_offset_uv, cali_trim; + + assert(vddq_uv >= 530000); + assert(vddq_uv <= 680000); + + /* Round down to multiple of 10 */ + target_mv = (vddq_uv / 1000) / 10 * 10; + + dram2_ori_mv = 600 - pmic_get_efuse_votrim() / 1000; + cali_offset_uv = 1000 * (target_mv - dram2_ori_mv); + + if (cali_offset_uv >= 80000) + cali_trim = 8; + else if (cali_offset_uv <= -70000) + cali_trim = 7; + else { + cali_trim = 0; + while (cali_trim < ARRAY_SIZE(vddq_votrim) && + vddq_votrim[cali_trim] != cali_offset_uv) + ++cali_trim; + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); + } + + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + pwrap_write_field(PMIC_VDDQ_ELR_0, cali_trim, 0xF, 0); + pwrap_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); + udelay(1); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0020, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + pwrap_write_field(PMIC_TOP_RST_MISC_CLR, 0x0002, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0001, 0xFFFF, 0); +} + +static void mt6366_init_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) + pwrap_write_field( + init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); +} + +static void wk_sleep_voltage_by_ddr(void) +{ + if (pwrap_read_field(PMIC_VM_MODE, 0x3, 0) == 0x2) + pwrap_write_field(PMIC_VDRAM1_VOSEL_SLEEP, 0x3A, 0x7F, 0); +} + +static void wk_power_down_seq(void) +{ + /* Write TMA KEY with magic number */ + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + /* Set VPROC12 sequence to VA12 */ + pwrap_write_field(PMIC_CPSDSA4, 0xA, 0x1F, 0); + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x0, 0xFFFF, 0); +} + +static void mt6366_lp_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) + pwrap_write_field( + lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} + +static void pmic_check_hwcid(void) +{ + printk(BIOS_WARNING, "%s: ID = %#x \n", __func__, + pwrap_read_field(0x8, 0xFFFF, 0)); +} + +void mt6366_set_power_hold(bool enable) +{ + pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); +} + +void mt6366_init_scp_voltage(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++) + pwrap_write_field( + scp_setting[i].addr, scp_setting[i].val, + scp_setting[i].mask, scp_setting[i].shift); +} + +void mt6366_set_vsim2_cali_mv(u32 vsim2_mv) +{ + u16 vsim2_reg, cali_mv; + + cali_mv = vsim2_mv % 100; + assert(cali_mv % 10 == 0); + + switch (vsim2_mv - cali_mv) { + case 1700: + vsim2_reg = 0x3; + break; + case 1800: + vsim2_reg = 0x4; + break; + case 2700: + vsim2_reg = 0x8; + break; + case 3000: + vsim2_reg = 0xb; + break; + case 3100: + vsim2_reg = 0xc; + break; + default: + BUG(); + return; + }; + + /* [11:8]=0x8, RG_VSIM2_VOSEL */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, vsim2_reg, 0xF, 8); + + /* [3:0], RG_VSIM2_VOCAL */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0); +} + +void mt6366_set_voltage(enum mt6366_regulator_id id, u32 voltage_uv) +{ + switch (id) { + case MT6366_VCORE: + pmic_set_vcore_vol(voltage_uv); + break; + case MT6366_VDRAM1: + pmic_set_vdram1_vol(voltage_uv); + break; + case MT6366_VDDQ: + pmic_set_vddq_vol(voltage_uv); + break; + default: + printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); + break; + } +} + +u32 mt6366_get_voltage(enum mt6366_regulator_id id) +{ + switch (id) { + case MT6366_VCORE: + return pmic_get_vcore_vol(); + case MT6366_VDRAM1: + return pmic_get_vdram1_vol(); + case MT6366_VDDQ: + return pmic_get_vddq_vol(); + default: + printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); + break; + } + return 0; +} + +void mt6366_init(void) +{ + struct stopwatch voltage_settled; + + if (pwrap_init()) + die("ERROR - Failed to initialize pmic wrap!"); + + pmic_check_hwcid(); + mt6366_set_power_hold(true); + pmic_wdt_set(); + mt6366_init_setting(); + stopwatch_init_usecs_expire(&voltage_settled, 200); + wk_sleep_voltage_by_ddr(); + wk_power_down_seq(); + mt6366_lp_setting(); + while (!stopwatch_expired(&voltage_settled)) + /* wait for voltages to settle */; +} diff --git a/src/soc/mediatek/mt8186/pmic_wrap.c b/src/soc/mediatek/mt8186/pmic_wrap.c new file mode 100644 index 0000000..17235d4 --- /dev/null +++ b/src/soc/mediatek/mt8186/pmic_wrap.c @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pmic_wrap.h> +#include <timer.h> + +#define PRIORITY_FIELD(x) ((x % 4) * 8) +#define PRIORITY_IN(id, priority) (id << PRIORITY_FIELD(priority)) +#define PRIORITY_OUT(id, priority) (priority << PRIORITY_FIELD(id)) + +enum { + MD_ADCINF0 = 8, + MD_ADCINF1 = 9, + STAUPD = 10, + GPSINF0 = 11, + + PRIORITY_IN_SEL_2 = PRIORITY_IN(MD_ADCINF0, 9) | + PRIORITY_IN(MD_ADCINF1, 10) | + PRIORITY_IN(STAUPD, 8) | + PRIORITY_IN(GPSINF0, 11), + + PRIORITY_OUT_SEL_2 = PRIORITY_OUT(MD_ADCINF0, 9) | + PRIORITY_OUT(MD_ADCINF1, 10) | + PRIORITY_OUT(STAUPD, 8) | + PRIORITY_OUT(GPSINF0, 11), +}; + +#define PENDING_US(x) x +enum { + STARVE_ENABLE = 0x1 << 10, + COUNTER0_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x2), + COUNTER1_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x3), + COUNTER2_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x3), + COUNTER3_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x3), + COUNTER4_PENDING_THRES = STARVE_ENABLE | PENDING_US(0xf), + COUNTER5_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x20), + COUNTER6_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x28), + COUNTER7_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x28), + COUNTER8_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x13), + COUNTER9_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x17), + COUNTER10_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x17), + COUNTER11_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x7c), + COUNTER12_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x7c), + COUNTER13_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340), + COUNTER16_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340), +}; + +static void pwrap_soft_reset(void) +{ + write32(&mt8186_infracfg_ao->infra_globalcon_rst2_set, 0x1); + write32(&mt8186_infracfg_ao->infra_globalcon_rst2_clr, 0x1); +} + +static void pwrap_spi_clk_set(void) +{ + write32(&mt8186_infracfg_ao->module_sw_cg_0_set, 0x0000000f); + write32(&mt8186_infracfg_ao->module_sw_cg_2_set, 0x00000100); + + write32(&mtk_topckgen->clk_cfg_8_clr, 0x00970000); + write32(&mtk_topckgen->clk_cfg_8_set, 0x00040000); + write32(&mtk_topckgen->clk_cfg_update1, (0x1 << 3)); + + write32(&mt8186_infracfg_ao->pmicw_clock_ctrl, + read32(&mt8186_infracfg_ao->pmicw_clock_ctrl) & ~(0x1 << 2)); + + pwrap_soft_reset(); + + write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x0000000f); + write32(&mt8186_infracfg_ao->module_sw_cg_2_clr, 0x00000100); +} + +static s32 pwrap_init_dio(u16 dio_en) +{ + pwrap_write_nochk(PMIC_DEW_DIO_EN, dio_en); + + if (!wait_us(100, + !wait_for_idle_and_sync(read32(&mtk_pwrap->wacs2_rdata)))) + return -1; + + write32(&mtk_pwrap->dio_en, dio_en); + return 0; +} + +static void pwrap_lock_spislvreg(void) +{ + pwrap_write_nochk(PMIC_SPISLV_KEY, 0x0); +} + +static void pwrap_initstaupd(void) +{ + write32(&mtk_pwrap->staupd_grpen, + SIG_PMIC_0 | INT_STA_PMIC_0 | MD_ADC_DATA0 | + MD_ADC_DATA1 | GPS_ADC_DATA0 | GPS_ADC_DATA1); + + /* CRC */ + pwrap_write_nochk(PMIC_DEW_CRC_EN, 0x1); + write32(&mtk_pwrap->crc_en, 0x1); + write32(&mtk_pwrap->sig_adr, PMIC_DEW_CRC_VAL); + + write32(&mtk_pwrap->eint_sta0_adr, PMIC_CPU_INT_STA); + + /* MD ADC Interface */ + write32(&mtk_pwrap->md_auxadc_rdata_latest_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + write32(&mtk_pwrap->md_auxadc_rdata_wp_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + for (size_t i = 0; i < 32; i++) + write32(&mtk_pwrap->md_auxadc_rdata[i], + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + + write32(&mtk_pwrap->int_gps_auxadc_cmd_addr, + (PMIC_AUXADC_RQST1 << 16) + PMIC_AUXADC_RQST0); + write32(&mtk_pwrap->int_gps_auxadc_cmd, (GPS_MAIN << 16) + GPS_SUBSYS); + write32(&mtk_pwrap->int_gps_auxadc_rdata_addr, + (PMIC_AUXADC_ADC32 << 16) + PMIC_AUXADC_ADC17); + + write32(&mtk_pwrap->ext_gps_auxadc_rdata_addr, PMIC_AUXADC_ADC31); +} + +static void pwrap_starve_set(void) +{ + write32(&mtk_pwrap->harb_hprio, ARB_PRIORITY); + write32(&mtk_pwrap->starv_counter_0, COUNTER0_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_1, COUNTER1_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_2, COUNTER2_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_3, COUNTER3_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_4, COUNTER4_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_5, COUNTER5_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_6, COUNTER6_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_7, COUNTER7_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_8, COUNTER8_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_9, COUNTER9_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_10, COUNTER10_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_11, COUNTER11_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_12, COUNTER12_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_13, COUNTER13_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_16, COUNTER16_PENDING_THRES); +} + +static void pwrap_enable(void) +{ + write32(&mtk_pwrap->hiprio_arb_en, ARB_USER_EN); + write32(&mtk_pwrap->wacs0_en, 0x1); + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->wacs_p2p_en, 0x1); + write32(&mtk_pwrap->wacs_md32_en, 0x1); + write32(&mtk_pwrap->staupd_ctrl, STA_PD_98_5_US); + write32(&mtk_pwrap->wdt_ctrl, WATCHDOG_TIMER_7_5_MS); + write32(&mtk_pwrap->wdt_src_en_0, WDT_MONITOR_ALL); + write32(&mtk_pwrap->wdt_src_en_1, WDT_MONITOR_ALL); + write32(&mtk_pwrap->timer_ctrl, 0x1); + write32(&mtk_pwrap->int0_en, INT0_MONITOR); + write32(&mtk_pwrap->int1_en, INT1_MONITOR); +} + +static s32 pwrap_init_sistrobe(void) +{ + u16 rdata; + int si_sample_ctrl; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pwrap->si_sample_ctrl, si_sample_ctrl << 5); + + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + /* + * Add the delay time of SPI data from PMIC to align the start boundary + * to current sampling clock edge. + */ + for (int si_dly = 0; si_dly < 10; si_dly++) { + pwrap_write_nochk(PMIC_RG_SPI_CON2, si_dly); + + int start_boundary_found = 0; + for (size_t i = 0; i < 30; i++) { + pwrap_write_nochk(PMIC_DEW_WRITE_TEST, test_data[i]); + pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + start_boundary_found = 1; + break; + } + } + if (start_boundary_found == 1) + break; + } + + /* + * Change the sampling clock edge to the next one which is the middle + * of SPI data window. + */ + write32(&mtk_pwrap->si_sample_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + pwrap_err("rdata = %#x, exp = %#x\n", rdata, + DEFAULT_VALUE_READ_TEST); + return E_PWR_READ_TEST_FAIL; + } + + return 0; +} + +static void pwrap_init_spislv(void) +{ + /* Turn on IO filter function */ + pwrap_write_nochk(PMIC_FILTER_CON0, SPI_FILTER); + /* Turn on IO SMT function to improve noise immunity */ + pwrap_write_nochk(PMIC_SMT_CON1, SPI_SMT); + /* Turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); + /* Enable SPI R/W in suspend mode */ + pwrap_write_nochk(PMIC_RG_SPI_CON0, 0x1); + /* Set PMIC GPIO driving current to 4mA */ + pwrap_write_nochk(PMIC_DRV_CON1, SPI_DRIVING); +} + +static void pwrap_init_reg_clock(void) +{ + write32(&mtk_pwrap->ext_ck_write, 0x1); + + pwrap_write_nochk(PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); + write32(&mtk_pwrap->rddmy, DUMMY_READ_CYCLES); + + write32(&mtk_pwrap->cshext_write, 0); + write32(&mtk_pwrap->cshext_read, 0); + write32(&mtk_pwrap->cslext_write, 0); + write32(&mtk_pwrap->cslext_read, 0); +} + +s32 pwrap_init(void) +{ + s32 sub_return = 0, sub_return1 = 0; + u16 rdata; + + pwrap_spi_clk_set(); + + /* Reset spislv */ + sub_return = pwrap_reset_spislv(); + if (sub_return != 0) { + pwrap_err("reset_spislv fail, ret=%d\n", sub_return); + return E_PWR_INIT_RESET_SPI; + } + + /* Enable WRAP */ + write32(&mtk_pwrap->wrap_en, 0x1); + + /* Enable WACS2 */ + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->hiprio_arb_en, WACS2); /* ONLY WACS2 */ + + /* SPI Waveform Configuration */ + pwrap_init_reg_clock(); + + /* SPI Slave Configuration */ + pwrap_init_spislv(); + + /* Enable DIO mode */ + sub_return = pwrap_init_dio(1); + if (sub_return != 0) { + pwrap_err("dio test error, ret=%d\n", sub_return); + return E_PWR_INIT_DIO; + } + + /* Input data calibration flow; */ + sub_return = pwrap_init_sistrobe(); + if (sub_return != 0) { + pwrap_err("InitSiStrobe fail,ret=%d\n", sub_return); + return E_PWR_INIT_SIDLY; + } + + /* + * Write test using WACS2, + * make sure the read/write function ready. + */ + sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST, WRITE_TEST_VALUE); + sub_return1 = pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if (rdata != WRITE_TEST_VALUE || sub_return || sub_return1) { + pwrap_err("write error, rdata=%#x, return=%d, return1=%d\n", + rdata, sub_return, sub_return1); + return E_PWR_INIT_WRITE_TEST; + } + + /* + * Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + pwrap_initstaupd(); + + write32(&mtk_pwrap->priority_user_sel_2, PRIORITY_IN_SEL_2); + write32(&mtk_pwrap->arbiter_out_sel_2, PRIORITY_OUT_SEL_2); + + pwrap_starve_set(); + + pwrap_enable(); + + /* Initialization Done */ + write32(&mtk_pwrap->init_done0, 0x1); + write32(&mtk_pwrap->init_done2, 0x1); + write32(&mtk_pwrap->init_done_p2p, 0x1); + write32(&mtk_pwrap->init_done_md32, 0x1); + + /* Lock SPISLV Registers */ + pwrap_lock_spislvreg(); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Gerrit-Change-Number: 59245 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021