coreboot-gerrit November 2021

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Change in coreboot[master]: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Andrey Pronin, Christian Walter, Tim Wawrzynczak, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59134 ) Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code ...................................................................... Patch Set 2: (1 comment) File src/security/tpm/tss/tcg-2.0/tss.c: https://review.coreboot.org/c/coreboot/+/59134/comment/20651f3a_09bbc2c2 PS2, Line 246: return TPM_E_READ_EMPTY; > How about TPM_E_READ_TOO_LARGE or TPM_E_REQUEST_TOO_LARGE? Why not just TPM_E_RANGE to match what it's called in the spec? (But either name is fine, I'm just saying it shouldn't overload the one that already means something else.) -- To view, visit https://review.coreboot.org/c/coreboot/+/59134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb Gerrit-Change-Number: 59134 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:53:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/trogdor: Adjust mipi panel backlight gpio
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: zanxi chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59044 ) Change subject: mb/google/trogdor: Adjust mipi panel backlight gpio ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/trogdor/mainboard.c: https://review.coreboot.org/c/coreboot/+/59044/comment/b2dc4ff9_cdf0cc76 PS5, Line 145: if (CONFIG(BOARD_GOOGLE_MRBLAND) || CONFIG(BOARD_GOOGLE_WORMDINGLER)) > Thanks, Julius. […] Yes, do use TROGDOR_HAS_MIPI_PANEL. All these boards should have the same layout. (If we later find out they don't we'll have to address that, but until we do let's assume we did it the right way.) -- To view, visit https://review.coreboot.org/c/coreboot/+/59044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a Gerrit-Change-Number: 59044 Gerrit-PatchSet: 6 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: xuxinxiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:47:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Add helper functions to look up size and type of a file
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Jakub Czapiga, Werner Zeh. Hello Jakub Czapiga, Werner Zeh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59312 to review the following change. Change subject: cbfs: Add helper functions to look up size and type of a file ...................................................................... cbfs: Add helper functions to look up size and type of a file This patch adds cbfs_get_size() and cbfs_get_type() helper functions (and _ro_ variations) to look up the size or type of a CBFS file without loading it. Generally, use of these should be discouraged because that tends to mean that the file needs to be looked up more than once, and cbfs_alloc() or cbfs_type_load() are usually the more efficient alternative... but sometimes they're unavoidable, so we might as well offer them. Also remove the <cbfs_private.h> header which had already become sort of unnecessary with previous changes. cbfs_boot_lookup() is now exported in <cbfs.h> for use in inlines, but should not be used directly by other files (and is prefixed with an underscore to highlight that). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba --- M src/include/cbfs.h D src/include/cbfs_private.h M src/lib/cbfs.c 3 files changed, 80 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/59312/1 diff --git a/src/include/cbfs.h b/src/include/cbfs.h index f6309a3..43d8123 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -7,6 +7,7 @@ #include <commonlib/bsd/cbfs_mdata.h> #include <commonlib/cbfs.h> #include <commonlib/mem_pool.h> +#include <commonlib/region.h> #include <program_loading.h> #include <types.h> #include <vb2_sha.h> @@ -119,6 +120,20 @@ /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); +/* Returns the size of a CBFS file, or 0 on error. Avoid using this function to allocate space, + and instead use cbfs_alloc() so the file only needs to be looked up once. */ +static inline size_t cbfs_get_size(const char *name); +static inline size_t cbfs_ro_get_size(const char *name); + +/* Returns the type of a CBFS file, or CBFS_TYPE_NULL on error. Use cbfs_type_load() instead of + this where possible to avoid looking up the file more than once. */ +static inline enum cbfs_type cbfs_get_type(const char *name); +static inline enum cbfs_type cbfs_ro_get_type(const char *name); + +/* Check whether a CBFS file exists. */ +static inline bool cbfs_file_exists(const char *name); +static inline bool cbfs_ro_file_exists(const char *name); + /********************************************************************************************** * BOOT DEVICE HELPER APIs * @@ -173,6 +188,9 @@ /********************************************************************************************** * INTERNAL HELPERS FOR INLINES, DO NOT USE. * **********************************************************************************************/ +cb_err_t _cbfs_boot_lookup(const char *name, bool force_ro, + union cbfs_mdata *mdata, struct region_device *rdev); + void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out, bool force_ro, enum cbfs_type *type); @@ -287,4 +305,58 @@ size_out, type); } +static inline size_t cbfs_get_size(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, false, &mdata, &rdev) != CB_SUCCESS) + return 0; + return be32toh(mdata.h.len); +} + +static inline size_t cbfs_ro_get_size(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, true, &mdata, &rdev) != CB_SUCCESS) + return 0; + return be32toh(mdata.h.len); +} + +static inline enum cbfs_type cbfs_get_type(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, false, &mdata, &rdev) != CB_SUCCESS) + return CBFS_TYPE_NULL; + return be32toh(mdata.h.type); +} + +static inline enum cbfs_type cbfs_ro_get_type(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, true, &mdata, &rdev) != CB_SUCCESS) + return CBFS_TYPE_NULL; + return be32toh(mdata.h.type); +} + +static inline bool cbfs_file_exists(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, false, &mdata, &rdev) != CB_SUCCESS) + return false; + return true; +} + +static inline bool cbfs_ro_file_exists(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, true, &mdata, &rdev) != CB_SUCCESS) + return false; + return true; +} + #endif diff --git a/src/include/cbfs_private.h b/src/include/cbfs_private.h deleted file mode 100644 index 8e98036..0000000 --- a/src/include/cbfs_private.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CBFS_PRIVATE_H_ -#define _CBFS_PRIVATE_H_ - -#include <commonlib/bsd/cbfs_private.h> -#include <commonlib/region.h> -#include <types.h> - -/* - * This header contains low-level CBFS APIs that should only be used by code - * that really needs this level of access. Most code (particularly platform - * code) should use the higher-level CBFS APIs in <cbfs.h>. Code using these - * APIs needs to take special care to ensure CBFS file data is verified (in a - * TOCTOU-safe manner) before access (TODO: add details on how to do this once - * file verification code is in). - */ - -/* Find by name, load metadata into |mdata| and chain file data to |rdev|. */ -cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, - union cbfs_mdata *mdata, struct region_device *rdev); - -#endif diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dbb3b1a..1ffc695 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,8 +3,8 @@ #include <assert.h> #include <boot_device.h> #include <cbfs.h> -#include <cbfs_private.h> #include <cbmem.h> +#include <commonlib/bsd/cbfs_private.h> #include <commonlib/bsd/compression.h> #include <commonlib/endian.h> #include <console/console.h> @@ -35,8 +35,8 @@ } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); -cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, - union cbfs_mdata *mdata, struct region_device *rdev) +cb_err_t _cbfs_boot_lookup(const char *name, bool force_ro, + union cbfs_mdata *mdata, struct region_device *rdev) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); if (!cbd) @@ -65,7 +65,7 @@ if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && err == CB_CBFS_NOT_FOUND) { printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", name); - return cbfs_boot_lookup(name, true, mdata, rdev); + return _cbfs_boot_lookup(name, true, mdata, rdev); } if (err) { if (err == CB_CBFS_NOT_FOUND) @@ -90,7 +90,7 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - if (cbfs_boot_lookup(name, false, &fh->mdata, &fh->data)) + if (_cbfs_boot_lookup(name, false, &fh->mdata, &fh->data)) return -1; size_t msize = be32toh(fh->mdata.h.offset); @@ -330,7 +330,7 @@ DEBUG("%s(name='%s')\n", __func__, name); - if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) + if (_cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) return; size = region_device_sz(&rdev); @@ -422,7 +422,7 @@ DEBUG("%s(name='%s', alloc=%p(%p), force_ro=%s, type=%d)\n", __func__, name, allocator, arg, force_ro ? "true" : "false", type ? *type : -1); - if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) + if (_cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) return NULL; if (type) { @@ -525,7 +525,7 @@ prog_locate_hook(pstage); - if ((err = cbfs_boot_lookup(prog_name(pstage), false, &mdata, &rdev))) + if ((err = _cbfs_boot_lookup(prog_name(pstage), false, &mdata, &rdev))) return err; assert(be32toh(mdata.h.type) == CBFS_TYPE_STAGE); -- To view, visit https://review.coreboot.org/c/coreboot/+/59312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba Gerrit-Change-Number: 59312 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: add list of gpios to lock
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58353 ) Change subject: mb/google/brya: add list of gpios to lock ...................................................................... Patch Set 14: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/gpio.c: https://review.coreboot.org/c/coreboot/+/58353/comment/dd6abb0c_fd03e71c PS11, Line 466: }; > Does the latest update cover it, or have you thought of any others I may have missed / that we shoul […] LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/58353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d Gerrit-Change-Number: 58353 Gerrit-PatchSet: 14 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:31:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz
by Selma Bensaid (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Bora Guvendik, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58373 ) Change subject: mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Could someone please +2 this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/58373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Gerrit-Change-Number: 58373 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:29:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add generic gpio lock mechanism
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Bora Guvendik, Caveh Jalali, Selma Bensaid, Maulik V Vaghela, Subrata Banik, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58351 ) Change subject: soc/intel/common: add generic gpio lock mechanism ...................................................................... Patch Set 11: Code-Review+2 (2 comments) File src/soc/intel/common/block/smm/Kconfig: https://review.coreboot.org/c/coreboot/+/58351/comment/196f6fb8_68b83acf PS10, Line 15: > suggestion: add a little bit more here about the fact that the SoC can provide […] Done File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/58351/comment/5ab15f4b_6f16beea PS10, Line 375: controllable by a non-host controller > I'd leave this part out, other people might have other reasons for wanting to lock GPIOs. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Gerrit-Change-Number: 58351 Gerrit-PatchSet: 11 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boris Mittelberg <bmbm(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:29:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Use dedicated VBT files for ADL-M
by Selma Bensaid (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Tim Wawrzynczak. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58202 ) Change subject: mb/intel/adlrvp: Use dedicated VBT files for ADL-M ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58202/comment/85b73d1e_b1872959 PS3, Line 12: VBT files added at chrome-internal:4138272 > So far the consensus seems to be that VBTs aren't in any way worthy of the amount of secrecy necessa […] These VBT are HW specific, not sure what is the advantage of making them public. Could we merge this to unblock ADL-M RVP and discuss access VBT or any other ingredients open sourcing through a Ticket? -- To view, visit https://review.coreboot.org/c/coreboot/+/58202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Gerrit-Change-Number: 58202 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:28:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Correct SSD power sequence
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ariel Fang, Malik Hsu, Casper Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59303 ) Change subject: mb/google/brya/variants/primus: Correct SSD power sequence ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59303/comment/cf0aa641_c10b9822 PS2, Line 10: SSD_PREST `SSD_PERST#` -- To view, visit https://review.coreboot.org/c/coreboot/+/59303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Gerrit-Change-Number: 59303 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:28:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Hook up two missing sensors
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58970 ) Change subject: mb/google/brya/var/redrix: Hook up two missing sensors ...................................................................... mb/google/brya/var/redrix: Hook up two missing sensors Redrix has 4 thermal sensors, so add the missing sensors settings. BUG=b:200134784 TEST=build and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Sumeet R Pawnikar: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index ce9ba37..77e44e3 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -86,13 +86,18 @@ chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""SOC"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 55, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 45, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 51, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 51, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 51, 5000), }" register "controls.power_limits" = "{ .pl1 = { -- To view, visit https://review.coreboot.org/c/coreboot/+/58970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Gerrit-Change-Number: 58970 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59310/comment/18c313fd_786dc31a PS1, Line 12: Also, modified `pch_get_ltt_value()` return type from uint16_t to : uint32_t > Sure Angel, i have thought that but later ignored, but make sense. Will update the CL. CB:59311 FYI -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 18:05:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021