coreboot-gerrit November 2021

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Change in coreboot[master]: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58962 ) Change subject: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/lib/prog_loaders.c: https://review.coreboot.org/c/coreboot/+/58962/comment/6f9035da_16324fa3 PS1, Line 133: return; nit: not sure why I didn't mention this first time this patch came around, but I think think this `return` could be a `dead_code()`. Platform code should not link in this function unless it actually intends to do preloading. Using dead_code() would enforce that at build time. -- To view, visit https://review.coreboot.org/c/coreboot/+/58962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Gerrit-Change-Number: 58962 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/mainboard/herobrine: Initialize SPI FW for EC and TPM
by Shelley Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner, Rajesh Patil. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50581 ) Change subject: mb/mainboard/herobrine: Initialize SPI FW for EC and TPM ...................................................................... Patch Set 88: (1 comment) File src/mainboard/google/herobrine/Kconfig: https://review.coreboot.org/c/coreboot/+/50581/comment/45eae99b_8de3b424 PS84, Line 66: default 0xC if BOARD_GOOGLE_HEROBRINE > ...why wouldn't it? It's true exactly iff you're building for Herobrine (the reference board). […] Sorry for not being clear. I meant that the Herobrine reference board should be using I2C communication for TPM rather than SPI. Only Hoglin/Piglin are using SPI with TPM. Agree with the rest of the what Julius said. -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 88 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:50:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/mainboard/herobrine: Initialize SPI FW for EC and TPM
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Rajesh Patil. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50581 ) Change subject: mb/mainboard/herobrine: Initialize SPI FW for EC and TPM ...................................................................... Patch Set 88: (1 comment) File src/mainboard/google/herobrine/Kconfig: https://review.coreboot.org/c/coreboot/+/50581/comment/3554b8f7_385b2620 PS84, Line 66: default 0xC if BOARD_GOOGLE_HEROBRINE > I think that this should never be true? ...why wouldn't it? It's true exactly iff you're building for Herobrine (the reference board). But, honestly, this stuff should allow a default case rather than requiring every board to be specified exactly. Piglin and Hoglin are the odd ones out, everything else should follow the layout of the Herobrine reference design. So this should be written as hex default 0xE if BOARD_GOOGLE_PIGLIN || BOARD_GOOGLE_HOGLIN default 0xC and then you won't need to update it every time someone adds a new Herobrine variant. (Same goes for EC_GOOGLE_CHROMEEC_SPI_BUS.) -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 88 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:41:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add NVRAM counter for TPM 2.0
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Miriam Polzer, Andrey Pronin, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59097 ) Change subject: security/vboot: Add NVRAM counter for TPM 2.0 ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: LGTM now but it would be good if Andrey also takes a look. -- To view, visit https://review.coreboot.org/c/coreboot/+/59097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1 Gerrit-Change-Number: 59097 Gerrit-PatchSet: 6 Gerrit-Owner: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Miriam Polzer <mpolzer(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:30:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by Shelley Chen (Code Review) 15 Nov '21

15 Nov '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: Add CPUCP firmware support ...................................................................... sc7280: Add CPUCP firmware support CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/cpucp_load_reset.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/cpucp.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 7 files changed, 101 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 953acc2..7f3cfbb 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -24,5 +24,6 @@ DECLARE_REGION(dram_wlan) DECLARE_REGION(dram_wpss) DECLARE_REGION(shrm) +DECLARE_REGION(dram_cpucp) #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 37ed21e..72fb57f 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += cbmem.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ramstage-y += ../common/aop_load_reset.c +ramstage-y += cpucp_load_reset.c ################################################################################ @@ -112,6 +113,14 @@ cbfs-files-y += $(AOP_CBFS) ################################################################################ +CPUCP_FILE := $(SC7280_BLOB)/cpucp/cpucp.elf +CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp +$(CPUCP_CBFS)-file := $(CPUCP_FILE) +$(CPUCP_CBFS)-type := payload +$(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_CBFS) + +################################################################################ SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm $(SHRM_CBFS)-file := $(SHRM_FILE) diff --git a/src/soc/qualcomm/sc7280/cpucp_load_reset.c b/src/soc/qualcomm/sc7280/cpucp_load_reset.c new file mode 100644 index 0000000..48b4707 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cpucp_load_reset.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <delay.h> +#include <cbfs.h> +#include <console/console.h> +#include <soc/mmu.h> +#include <soc/cpucp.h> +#include <soc/clock.h> +#include <device/mmio.h> +#include <timer.h> + +void cpucp_prepare(void) +{ + /* allow NS access to EPSS memory*/ + setbits32(&epss_top->access_override, 0x1); + + /* Enable subsystem clock. Required for CPUCP PDMEM access*/ + setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1); + if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1))) + printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__); +} + +void cpucp_fw_load_reset(void) +{ + struct prog cpucp_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); + + cpucp_prepare(); + + if (!selfload(&cpucp_fw_prog)) + die("SOC image: CPUCP load failed"); + + printk(BIOS_DEBUG, "SOC:CPUCP image loaded successfully.\n"); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 599d03f..8515a04 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -55,4 +55,7 @@ #define QUP_WRAP1_BASE 0x00AC0000 #define QUP_1_GSI_BASE 0x00A04000 +#define EPSSTOP_EPSS_TOP 0x18598000 +#define EPSSFAST_BASE_ADDR 0x18580000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/cpucp.h b/src/soc/qualcomm/sc7280/include/soc/cpucp.h new file mode 100644 index 0000000..37ae7d2 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/cpucp.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_CPUCP_H__ +#define _SOC_QUALCOMM_SC7280_CPUCP_H__ + +#include <soc/addressmap.h> + +struct epsstop_epss_top { + uint32_t access_override; + uint32_t global_enable; + uint32_t trace_bus_ctrl; + uint32_t debug_bus_ctrl; + uint32_t muc_hang_det_ctrl; + uint32_t muc_hang_irq_sts; + uint32_t muc_hang_count_threshold; + uint32_t muc_hang_count_sts; + uint32_t muc_hang_det_sts; + uint32_t l3_voting_en; +}; + +struct epssfast_epss_fast { + uint32_t epss_muc_clk_ctrl; + uint32_t muc_rvbar; + uint32_t muc_rvbar_ctrl; + uint32_t muc_non_secure_dmem_start_addr; + uint32_t muc_non_secure_dmem_end_addr; + uint32_t reserved_1[2]; + uint32_t cpr_data_fifo[4]; + uint32_t reserved_2[4]; + uint32_t pll_data_fifo[4]; + uint32_t reserved_3[4]; + uint32_t gfmux_data_fifo_1[4]; + uint32_t cpu_pcu_spare_irq_status; + uint32_t cpu_pcu_spare_irq_clr; + uint32_t cpu_pcu_spare_wait_event; + uint32_t seq_mem[256]; +}; + +static struct epsstop_epss_top *const epss_top = (void *)EPSSTOP_EPSS_TOP; +static struct epssfast_epss_fast *const epss_fast = (void *)EPSSFAST_BASE_ADDR; + +void cpucp_fw_load_reset(void); +void cpucp_prepare(void); + +#endif // _SOC_QUALCOMM_SC7280_CPUCP_H__ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 620e5b5..57cdb59 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -54,9 +54,10 @@ /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x080000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) - BL31(0x80B00000, 1M) + REGION(dram_cpucp,0x80B00000, 0x100000, 0x1000) REGION(dram_wlan, 0x80C00000, 0xC00000, 0x1000) REGION(dram_wpss, 0x9AE00000, 0x1900000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) + BL31(0xC0000000, 1M) } diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index ff2b7cc..8d27a46 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -5,6 +5,7 @@ #include <soc/mmu_common.h> #include <soc/symbols_common.h> #include <soc/aop_common.h> +#include <soc/cpucp.h> static void soc_read_resources(struct device *dev) { @@ -13,16 +14,19 @@ reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_wlan / KiB, - REGION_SIZE(dram_wlan) / KiB); + REGION_SIZE(dram_wlan) / KiB); reserved_ram_resource(dev, 3, (uintptr_t)_dram_wpss / KiB, - REGION_SIZE(dram_wpss) / KiB); + REGION_SIZE(dram_wpss) / KiB); reserved_ram_resource(dev, 4, (uintptr_t)_dram_aop / KiB, REGION_SIZE(dram_aop) / KiB); + reserved_ram_resource(dev, 5, (uintptr_t)_dram_cpucp / KiB, + REGION_SIZE(dram_cpucp) / KiB); } static void soc_init(struct device *dev) { aop_fw_load_reset(); + cpucp_fw_load_reset(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 90 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by Shelley Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: Add CPUCP firmware support ...................................................................... Patch Set 89: (2 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: https://review.coreboot.org/c/coreboot/+/49768/comment/642d5327_1495dc12 PS80, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); > Just use setbits32() to do this in one line. Done File src/soc/qualcomm/sc7280/include/soc/cpucp.h: https://review.coreboot.org/c/coreboot/+/49768/comment/f0aa5d6a_c3e443c4 PS86, Line 6: #define EPSSTOP_EPSS_TOP (void *)0x18598000 > These should go into <soc/addressmap.h> (and we don't usually put the (void *) cast in the macro). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 89 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by Julius Werner (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: Add CPUCP firmware support ...................................................................... Patch Set 89: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 89 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:26:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Bora Guvendik, Maulik V Vaghela, Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58373 ) Change subject: mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Gerrit-Change-Number: 58373 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:02:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Include SPD for MT53E512M32D1NP-046 WT:B a...
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: YH Lin, Furquan Shaikh, Caveh Jalali, Angel Pons, Nick Vaccaro, Mark Hsieh, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59299 ) Change subject: mb/google/brya/var/gimble: Include SPD for MT53E512M32D1NP-046 WT:B and MT53E1G32D2NP-046 WT:B ...................................................................... Patch Set 4: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59299/comment/10af2e7d_7b69ccdb PS4, Line 6: : mb/google/brya/var/gimble: Include SPD for MT53E512M32D1NP-046 WT:B and MT53E1G32D2NP-046 WT:B : suggestion: `mb/google/brya/gimble: Include 2 new SPDs` https://review.coreboot.org/c/coreboot/+/59299/comment/69fecc9e_2fcce3f0 PS4, Line 9: Add SPD support to gimble for LPDDR4 memory part MT53E512M32D1NP-046 WT:B and MT53E1G32D2NP-046 WT:B. : : BUG=b:191574298 : TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. : 72 characters wide -- To view, visit https://review.coreboot.org/c/coreboot/+/59299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab Gerrit-Change-Number: 59299 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 21:01:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Shelley Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56091 ) Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... Patch Set 37: (1 comment) Patchset: PS37: Looks like Jenkins is unhappy: src/soc/qualcomm/common/include/soc/usb/qusb_phy.h has multiple final newlines. src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h has multiple final newlines. -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 20:59:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021