coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/adl: Enable GPIO PM after booting to OS
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Mark Hsieh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59264 ) Change subject: soc/intel/adl: Enable GPIO PM after booting to OS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Won't this cause the same problem whether it's enabled by the BIOS or by ASL after the kernel starts? The cr50 pulses will be missed and communication is slowed or missed -- To view, visit https://review.coreboot.org/c/coreboot/+/59264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5be925caace7a58052476d0995fb9ee0efc2fd2 Gerrit-Change-Number: 59264 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 23:13:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Karthik Ramasubramanian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59134 ) Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code ...................................................................... Abandoned Human Error during upload. -- To view, visit https://review.coreboot.org/c/coreboot/+/59134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb Gerrit-Change-Number: 59134 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: security/vboot: Use default kernel secdata size
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian. Karthik Ramasubramanian has uploaded a new patch set (#6) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/58669 ) Change subject: security/vboot: Use default kernel secdata size ...................................................................... security/vboot: Use default kernel secdata size When fetching antirollback information for the kernel, it is not always known ahead of time what the current size of the kernel secdata area is. If the incorrect size is passed, the TPM will return back the correct size, but at the cost of an extra transaction; when using cr50 over I2C, this can be as much as 20ms. Currently, the first attempt uses the minimium size (aka version 0 or 0.2), and if another size is used (which is the case for all modern cr50-based boards, version 1 or 1.0), then a transaction is wasted on every boot. Therefore, change the default size sent to the TPM to be the default one used in the VB2 API instead of the minimum one. BUG=b:201304784 TEST=verify TPM initialization time drops by ~20ms. Also the Kernel NV Index is read correctly in the BIOS logs. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 504:finished TPM initialization 99,953 (65,606) Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/secdata_tpm.c 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58669/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Gerrit-Change-Number: 58669 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Andrey Pronin, Christian Walter, Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Andrey Pronin, Raul Rangel, Christian Walter, Julius Werner, Tim Wawrzynczak, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59134 to look at the new patch set (#3). Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code ...................................................................... security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code As per the TPM spec, if offset and the size field of data add to a value that is greater than the dataSize field of the NV Index referenced by nvIndex, the TPM shall return an error (TPM_RC_NV_RANGE). Handle the TPM error and map it to an appropriate vboot error. BUG=None TEST=Build and boot to OS in Guybrush. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb --- M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss_errors.h 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59134/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb Gerrit-Change-Number: 59134 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Christian Walter. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59319 ) Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code ...................................................................... security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code As per the TPM spec, if offset and the size field of data add to a value that is greater than the dataSize field of the NV Index referenced by nvIndex, the TPM shall return an error (TPM_RC_NV_RANGE). Handle the TPM error and map it to an appropriate vboot error. BUG=None TEST=Build and boot to OS in Guybrush. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb Squash Change-Id: I8ef354d5ffc6093d34b47c11c288909d69e5cd51 --- M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss_errors.h 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59319/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index cfa533b..8c9d12f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -242,6 +242,9 @@ case TPM_RC_CR50_NV_UNDEFINED: return TPM_E_BADINDEX; + case TPM_RC_NV_RANGE: + return TPM_E_RANGE; + default: return TPM_E_READ_FAILURE; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index cb8b4f9..c0e354d 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -144,6 +144,7 @@ /* Values copied from tpm2/tpm_types.h */ #define RC_VER1 0x100 #define TPM_RC_INITIALIZE ((TPM_RC)(RC_VER1 + 0x000)) +#define TPM_RC_NV_RANGE ((TPM_RC)(RC_VER1 + 0x046)) #define TPM_RC_NV_UNINITIALIZED ((TPM_RC)(RC_VER1 + 0x04A)) /* diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index 7c4e569..49a7405 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -41,5 +41,6 @@ #define TPM_E_INVALID_ARG ((uint32_t)0x0000500c) #define TPM_E_HASH_ERROR ((uint32_t)0x0000500d) #define TPM_E_NO_SUCH_COMMAND ((uint32_t)0x0000500e) +#define TPM_E_RANGE ((uint32_t)0x0000500f) #endif /* TSS_ERRORS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ef354d5ffc6093d34b47c11c288909d69e5cd51 Gerrit-Change-Number: 59319 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Use default kernel secdata size
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Yu-Ping Wu, Andrey Pronin, Karthik Ramasubramanian. Karthik Ramasubramanian has uploaded a new patch set (#5) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/58669 ) Change subject: security/vboot: Use default kernel secdata size ...................................................................... security/vboot: Use default kernel secdata size When fetching antirollback information for the kernel, it is not always known ahead of time what the current size of the kernel secdata area is. If the incorrect size is passed, the TPM will return back the correct size, but at the cost of an extra transaction; when using cr50 over I2C, this can be as much as 20ms. Currently, the first attempt uses the minimium size (aka version 0 or 0.2), and if another size is used (which is the case for all modern cr50-based boards, version 1 or 1.0), then a transaction is wasted on every boot. Therefore, change the default size sent to the TPM to be the default one used in the VB2 API instead of the minimum one. BUG=b:201304784 TEST=verify TPM initialization time drops by ~20ms. Also the Kernel NV Index is read correctly in the BIOS logs. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 504:finished TPM initialization 99,953 (65,606) Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/secdata_tpm.c 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/58669/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/58669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Gerrit-Change-Number: 58669 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Varshit B Pandya, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... Patch Set 10: (1 comment) File src/drivers/intel/mipi_camera/chip.h: https://review.coreboot.org/c/coreboot/+/58767/comment/a2b82f17_c80ea499 PS10, Line 260: uint8_t max_dstate_for_probe; > not sure if you would like to add an ascii table to let users know abut the possible configurations […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 10 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 23:08:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: Add CRFI field into globalnvs
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Saurabh Mishra, Maulik V Vaghela, Ravindra, Sumeet R Pawnikar, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Tim Wawrzynczak, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58323 ) Change subject: intel/common/block: Add CRFI field into globalnvs ...................................................................... Patch Set 6: Code-Review-1 (1 comment) Patchset: PS6: see patch on top, NVS is not necessary -- To view, visit https://review.coreboot.org/c/coreboot/+/58323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c64ae7a220c1551f2c61ab92c0ca0ec8b235745 Gerrit-Change-Number: 58323 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 23:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add _DSM method for CNVi WiFi
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Saurabh Mishra, Maulik V Vaghela, Sumeet R Pawnikar, Ravindra, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Tim Wawrzynczak, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58324 ) Change subject: soc/intel/alderlake: Add _DSM method for CNVi WiFi ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/acpi/cnvi_wifi.asl: PS7: This should be generated at runtime using the acpigen library; therefore this should go in `drivers/wifi/generic/acpi.c`, then the NVS is not required. When you generate the AML at runtime, many of the reasons for NVS disappear 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/58324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb234d4e2e3f60d65fa76d41db4c7eea6324437 Gerrit-Change-Number: 58324 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 23:07:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58132 ) Change subject: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration ...................................................................... Patch Set 6: (2 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/58132/comment/6b2b1528_9be51613 PS6, Line 532: /* CNVi DDR RFIM Enable/Disable : * Default 0. Setting this to 1 disables CNVi DDR RFIM. : */ : bool CnviDdrRfimDisable; I think we should invert the polarity of this, and have it be an `Enable` option File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/58132/comment/8199b58f_3959a9ed PS6, Line 211: (config->CnviDdrRfimDisable) nit: parentheses not required -- To view, visit https://review.coreboot.org/c/coreboot/+/58132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Gerrit-Change-Number: 58132 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 23:04:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021