coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/taeko: disabled autonomous GPIO power management
by Joey Peng (Code Review) 16 Nov '21

16 Nov '21

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59325 ) Change subject: mb/google/brya/var/taeko: disabled autonomous GPIO power management ...................................................................... mb/google/brya/var/taeko: disabled autonomous GPIO power management Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:205315500 TEST=emerge-brya coreboot and test that DUT can boot to OS. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/59325/1 diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index d6d7c9b..a482363 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -41,6 +41,16 @@ end end chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, -- To view, visit https://review.coreboot.org/c/coreboot/+/59325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Gerrit-Change-Number: 59325 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Update SPKR GPIO configuration
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Kevin Chiu, Bhanu Prakash Maiya, Eric Peers. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59051 ) Change subject: mb/google/guybrush/var/nipperkin: Update SPKR GPIO configuration ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/59051/comment/e217fb85_aac652b3 PS4, Line 87: PAD_NC(GPIO_70), Please configure the following GPIOs in the baseboard here. PAD_NC(GPIO_31), PAD_GPO(GPIO_70, HIGH) Please donot configure in the pcie_table. This signal needs to be set high only in ramstage In Guybrush - For Board ID2: PAD_GPO(GPIO_31, HIGH), PAD_NC(GPIO_70) In Nipperkin - For Board ID1: PAD_GPO(GPIO_31, HIGH), PAD_NC(GPIO_70) -- To view, visit https://review.coreboot.org/c/coreboot/+/59051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Gerrit-Change-Number: 59051 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 01:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/redrix: Configure Acoustic noise mitigation
by Chen Wisley (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak. Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58947 ) Change subject: mb/google/brya/var/redrix: Configure Acoustic noise mitigation ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/58947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8 Gerrit-Change-Number: 58947 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 01:01:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add Acoustic noise mitigation UPDs
by Chen Wisley (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Wisley Chen, Patrick Rudolph. Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58944 ) Change subject: soc/intel/alderlake: Add Acoustic noise mitigation UPDs ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/58944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Gerrit-Change-Number: 58944 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 01:01:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Correct SSD power sequence
by Casper Chang (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Ariel Fang, Malik Hsu. Casper Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59303 ) Change subject: mb/google/brya/variants/primus: Correct SSD power sequence ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59303/comment/02700451_a67712e3 PS2, Line 10: SSD_PREST > `SSD_PERST#` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Gerrit-Change-Number: 59303 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 00:39:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Correct SSD power sequence
by Casper Chang (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Ariel Fang, Malik Hsu, Casper Chang. Hello build bot (Jenkins), Ariel Fang, Malik Hsu, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59303 to look at the new patch set (#3). Change subject: mb/google/brya/variants/primus: Correct SSD power sequence ...................................................................... mb/google/brya/variants/primus: Correct SSD power sequence SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PERST# should be sequenced after power enable. BUG=b:199967106 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 --- M src/mainboard/google/brya/variants/primus/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59303/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Gerrit-Change-Number: 59303 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59053 ) Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default and only overriding to GPIO_70 for guybrush bid==1. BUG=b:202992077 BRANCH=None TEST=Build and boot guybrush, SD card works Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/helpers.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/guybrush/variant.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/variant.c 6 files changed, 19 insertions(+), 62 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 6b8c2b7..82956dc 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -21,8 +21,8 @@ PAD_GPO(GPIO_3, LOW), /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, HIGH), /* EN_PP3300_TCHPAD */ @@ -81,8 +81,8 @@ PAD_GPI(GPIO_67, PULL_NONE), /* EN_PP3300_TCHSCR */ PAD_GPO(GPIO_68, HIGH), - /* Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, HIGH), /* Unused TP27 */ PAD_NC(GPIO_70), /* GPIO_71 - GPIO_73: Not available */ @@ -170,16 +170,16 @@ /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { /* Assert all AUX reset lines */ - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, LOW), + /* Unused */ + PAD_NC(GPIO_5), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, LOW), /* WLAN_AUX_RESET (ACTIVE HIGH) */ PAD_GPO(GPIO_29, HIGH), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), - /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, LOW), /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ PAD_NC(GPIO_70), @@ -278,16 +278,16 @@ /* PCIE_RST needs to be brought high before FSP-M runs */ static const struct soc_amd_gpio pcie_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, HIGH), /* WLAN_AUX_RESET (ACTIVE HIGH) */ PAD_GPO(GPIO_29, LOW), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), - /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, HIGH), /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ PAD_NC(GPIO_70), /* PCIE_RST0_L */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c index 36f7b05..fe30e15 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -11,5 +11,5 @@ uint8_t __weak variant_sd_aux_reset_gpio(void) { - return GPIO_5; + return GPIO_69; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index bf8e999..6309ec2 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -31,8 +31,6 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { /* EN_PP5000_PEN */ PAD_GPO(GPIO_5, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ @@ -42,9 +40,6 @@ }; static const struct soc_amd_gpio override_early_gpio_table[] = { - PAD_NC(GPIO_5), - /* BID >= 2: SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, LOW), /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), /* GSC_SOC_INT_L */ @@ -55,18 +50,10 @@ /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { - PAD_NC(GPIO_5), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, HIGH), }; -/* This table is used by guybrush variant with board version < 2. */ -static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { - PAD_NC(GPIO_5), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), -}; - const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -101,6 +88,5 @@ return bid1_pcie_gpio_table; } - *size = ARRAY_SIZE(bid2_pcie_gpio_table); - return bid2_pcie_gpio_table; + return NULL; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c index ded1351..54ca6a0 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/variant.c +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <boardid.h> #include <device/device.h> #include <soc/gpio.h> @@ -11,5 +12,5 @@ uint8_t variant_sd_aux_reset_gpio(void) { - return GPIO_69; + return board_id() == 1 ? GPIO_70 : GPIO_69; } diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 4d6e045..2c502df 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -16,8 +16,6 @@ PAD_NC(GPIO_18), /* LCD_PRIVACY_PCH */ PAD_GPO(GPIO_5, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ @@ -34,30 +32,16 @@ PAD_NC(GPIO_17), /* LCD_PRIVACY_PCH */ PAD_GPO(GPIO_18, HIGH), - /* Unused */ - PAD_NC(GPIO_69), }; static const struct soc_amd_gpio override_early_gpio_table[] = { /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_NC(GPIO_18), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, LOW), }; -/* This table is used by nipperkin variant with board version < 2. */ -static const struct soc_amd_gpio bid1_override_pcie_gpio_table[] = { - PAD_NC(GPIO_5), +static const struct soc_amd_gpio override_pcie_gpio_table[] = { PAD_NC(GPIO_18), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), -}; - -/* This table is used by nipperkin variant with board version >= 2. */ -static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = { - PAD_NC(GPIO_18), - PAD_NC(GPIO_69), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -81,13 +65,6 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) { - uint32_t board_version = board_id(); - - if (board_version < 2) { - *size = ARRAY_SIZE(bid1_override_pcie_gpio_table); - return bid1_override_pcie_gpio_table; - } - - *size = ARRAY_SIZE(bid2_override_pcie_gpio_table); - return bid2_override_pcie_gpio_table; + *size = ARRAY_SIZE(override_pcie_gpio_table); + return override_pcie_gpio_table; } diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index 917857c..c53d691 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -10,10 +10,3 @@ dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false; } - -uint8_t variant_sd_aux_reset_gpio(void) -{ - uint32_t board_ver = board_id(); - - return (board_ver < 2) ? GPIO_69 : GPIO_5; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 5 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59295 ) Change subject: soc/mediatek: move i2c function to common folder ...................................................................... Patch Set 5: (2 comments) File src/soc/mediatek/common/i2c.c: https://review.coreboot.org/c/coreboot/+/59295/comment/b16b3145_95fe6f13 PS5, Line 35: { /* do nothing */ } Could you take the chance to fix this as well? https://review.coreboot.org/c/coreboot/+/59295/comment/c999d8b7_39f038fd PS5, Line 549: This function is only used from MT8195. No need to mention this in the common file. -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 00:24:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59134 ) Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb Gerrit-Change-Number: 59134 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 00:17:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Use default kernel secdata size
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Raul Rangel, Tim Wawrzynczak, Julius Werner, Andrey Pronin, Karthik Ramasubramanian. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58669 ) Change subject: security/vboot: Use default kernel secdata size ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Gerrit-Change-Number: 58669 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 00:17:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021