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Change subject: mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin
......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/59051/comment/5640c003_f0ba3290
PS5, Line 70: PAD_GPO(GPIO_31, HIGH),
> Please make this PAD_NC(GPIO_31)
Done
File src/mainboard/google/guybrush/variants/guybrush/gpio.c:
https://review.coreboot.org/c/coreboot/+/59051/comment/7f1d4202_fa6392b0
PS5, Line 13: PAD_NC(GPIO_31),
> nit: could be removed.
Done
File src/mainboard/google/guybrush/variants/nipperkin/gpio.c:
https://review.coreboot.org/c/coreboot/+/59051/comment/b81dec06_eecf89b1
PS5, Line 39: /* Unused */
> Override for GPIO_31 and GPIO_70 is not needed here because it matches base_gpio. Please remove.
Done
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Change subject: soc/intel/alderlake: Allow thermal configuration for ADL
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Do we need this as early as possible? Like rom-stage before MRC training to prevent some HW issue?
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Hello build bot (Jenkins), Bhanu Prakash Maiya, Rob Barnes, Eric Peers, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59051
to look at the new patch set (#6).
Change subject: mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin
......................................................................
mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin
For Guybrush Board Version 2, Nipperking Board Version 1,
update SPKR GPIO to match H/W schematic:
SPKR: GPIO31
For Nipperkin Board Version 2, update SPKR GPIO to
match H/W schematic:
SPKR: GPIO70
BUG=b:202992077
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
M src/mainboard/google/guybrush/variants/nipperkin/gpio.c
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
4 files changed, 13 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/59051/6
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59051 )
Change subject: mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin
......................................................................
Patch Set 5:
(3 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/59051/comment/f6d6e688_2ab3008a
PS5, Line 70: PAD_GPO(GPIO_31, HIGH),
Please make this PAD_NC(GPIO_31)
File src/mainboard/google/guybrush/variants/guybrush/gpio.c:
https://review.coreboot.org/c/coreboot/+/59051/comment/d53f730d_7990a45a
PS5, Line 13: PAD_NC(GPIO_31),
nit: could be removed.
File src/mainboard/google/guybrush/variants/nipperkin/gpio.c:
https://review.coreboot.org/c/coreboot/+/59051/comment/fceaf45c_0e9e2ecc
PS5, Line 39: /* Unused */
Override for GPIO_31 and GPIO_70 is not needed here because it matches base_gpio. Please remove.
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Change subject: mb/google/brya: Move typeC AUX configuration to variant
......................................................................
Patch Set 1: Code-Review+2
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Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59288 )
Change subject: mb/google/brya/var/vell: Generate LP5 RAM ID
......................................................................
mb/google/brya/var/vell: Generate LP5 RAM ID
Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I49745948ebdb25fd98e285defd75714f80271968
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Reka Norman <rekanorman(a)chromium.org>
---
M src/mainboard/google/brya/variants/vell/memory/Makefile.inc
M src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
3 files changed, 16 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
Reka Norman: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
index 6751a42..8288400 100644
--- a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
@@ -1,5 +1,8 @@
-## SPDX-License-Identifier: GPL-2.0-or-later
-## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/vell/memory src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B
diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
index fa24790..f029f6b 100644
--- a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
@@ -1 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/vell/memory src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
+
DRAM Part Name ID to assign
+MT62F512M32D2DR-031 WT:B 0 (0000)
+MT62F1G32D4DR-031 WT:B 1 (0001)
diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
index 9621137..3baf5d4 100644
--- a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
@@ -9,3 +9,5 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+MT62F512M32D2DR-031 WT:B
+MT62F1G32D4DR-031 WT:B
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Change subject: security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
......................................................................
Patch Set 4: Code-Review+1
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Change subject: security/vboot: Use default kernel secdata size
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/58669/comment/2a01298a_bd4e0f29
PS7, Line 68: Empty Kernel Secdata, Trying
nit: do any of these words need to be capitalized?
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Change subject: mb/google/hatch: Alphabetize variants in Kconfig.name
......................................................................
Patch Set 1: Code-Review+2
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