coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Rizwan Qureshi (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Reka Norman, Subrata Banik, Balaji Manigandan, Usha P, Tim Wawrzynczak, Patrick Rudolph, Kangheui Won. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/59306/comment/73906e9c_ed968629 PS1, Line 30: -N > may be make it as "Alderlake" alone like other does without additional overhead ? If everything is just going to be "Alderlake", do we even need this table? 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Kangheui Won <khwon(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 04:00:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Shon Wang. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59334 to look at the new patch set (#2). Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb --- M src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/memory.c 2 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 2 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Allow thermal configuration for ADL
by Felix Singer (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59271 ) Change subject: soc/intel/alderlake: Allow thermal configuration for ADL ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59271/comment/4a46e6f6_420a7078 PS3, Line 7: for ADL Not needed. Already mentioned in the first part. https://review.coreboot.org/c/coreboot/+/59271/comment/91fec063_78897f64 PS3, Line 7: Allow thermal configuration How about this: Hook up common code for thermal configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 03:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 16 Nov '21

16 Nov '21

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb --- M src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/memory.c 2 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/1 diff --git a/src/mainboard/google/brya/variants/vell/Makefile.inc b/src/mainboard/google/brya/variants/vell/Makefile.inc index 009117a..35286d1 100644 --- a/src/mainboard/google/brya/variants/vell/Makefile.inc +++ b/src/mainboard/google/brya/variants/vell/Makefile.inc @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c romstage-y += gpio.c -ramstage-y += gpio.c \ No newline at end of file +ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c new file mode 100644 index 0000000..6e36240 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera
by Robert Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Robert Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59333 to look at the new patch set (#2). Change subject: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera ...................................................................... mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera Add fw_config probe for MIPI camera BUG=b:2059201110 TEST=FW_NAME=drawcia emerge-dedede coreboot Change-Id: I89d84b6eb77c18b36b1ff946cec057889013c58f --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59333/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89d84b6eb77c18b36b1ff946cec057889013c58f Gerrit-Change-Number: 59333 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera
by build bot (Jenkins) (Code Review) 16 Nov '21

16 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59333 ) Change subject: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133377): https://review.coreboot.org/c/coreboot/+/59333/comment/a3a794f8_3f6c30e9 PS1, Line 333: device i2c 36 on trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133377): https://review.coreboot.org/c/coreboot/+/59333/comment/ac3f6c9a_592e42cc PS1, Line 355: device i2c 0C on trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133377): https://review.coreboot.org/c/coreboot/+/59333/comment/b557c19d_6bfde24f PS1, Line 381: device i2c 50 on trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/59333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89d84b6eb77c18b36b1ff946cec057889013c58f Gerrit-Change-Number: 59333 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 03:45:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera
by Robert Chen (Code Review) 16 Nov '21

16 Nov '21

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59333 ) Change subject: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera ...................................................................... mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera Add fw_config probe for MIPI camera BUG=b:2059201110 TEST=FW_NAME=drawcia emerge-dedede coreboot Change-Id: I89d84b6eb77c18b36b1ff946cec057889013c58f --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59333/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index cb3ff48..e141b74 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -89,7 +89,9 @@ register "cio2_lane_endpoint[1]" = ""^I2C3.CAM1"" register "cio2_prt[0]" = "0" register "cio2_prt[1]" = "2" - device generic 0 on end + device generic 0 on + probe TABLETMODE TABLETMODE_DISABLED + end end end @@ -328,7 +330,9 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 36 on end + device i2c 36 on + probe TABLETMODE TABLETMODE_ENABLED + end end chip drivers/intel/mipi_camera register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" @@ -348,7 +352,9 @@ #_OFF register "off_seq.ops_cnt" = "1" register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 0C on end + device i2c 0C on + probe TABLETMODE TABLETMODE_ENABLED + end end chip drivers/intel/mipi_camera register "acpi_uid" = "1" @@ -372,7 +378,9 @@ #_OFF register "off_seq.ops_cnt" = "1" register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 50 on end + device i2c 50 on + probe TABLETMODE TABLETMODE_ENABLED + end end end # I2C 3 device pci 19.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89d84b6eb77c18b36b1ff946cec057889013c58f Gerrit-Change-Number: 59333 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variants/kano: Support MIPI device probe in non-zero A...
by Jim Lai (Code Review) 16 Nov '21

16 Nov '21

Jim Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59332 ) Change subject: mb/google/brya/variants/kano: Support MIPI device probe in non-zero ACPI D state ...................................................................... mb/google/brya/variants/kano: Support MIPI device probe in non-zero ACPI D state Tell ACPI device PM code that the driver supports the device being in non-zero ACPI D state when the driver's probe function is entered. BUG=b:202277522 TEST=Build and boot on Kano Signed-off-by: Lai, Jim <jim.lai(a)intel.com> Change-Id: I166e85f9bd0727ea5a8ffb6b3e99c62b0b1c0ae5 --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/59332/1 diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 499dad2..4aaff01 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -352,6 +352,7 @@ register "acpi_name" = ""CAM0"" register "chip_name" = ""Ov 2740 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "acpi_dsc" = "1" register "has_power_resource" = "1" register "ssdb.lanes_used" = "2" @@ -391,8 +392,6 @@ register "chip_name" = ""AT24 EEPROM"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/59332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I166e85f9bd0727ea5a8ffb6b3e99c62b0b1c0ae5 Gerrit-Change-Number: 59332 Gerrit-PatchSet: 1 Gerrit-Owner: Jim Lai <jim.lai(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by EricR Lai (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 8: Code-Review+1 (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/84cf3315_b26a1e98 PS8, Line 106: /* Enable thermal sensor power management using PMC PCH device */ : static void pch_pmc_thermal_configuration(void) : { : struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); : uintptr_t pmc_bar = soc_read_pmc_base(); : : struct pmc_thermal_config { : void (*func)(uintptr_t addr, uint32_t data); : uint16_t offset; : uint32_t value; : } config[] = { : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_CTEN, : .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_ECRPTEN, : .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT : | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK, : }, : { : .func = write32p, : .offset = PMC_PWRM_THERMAL_TL, : .value = pch_get_ltt_value(dev) | PMC_PWRM_THERMAL_TL_TTEN : | PMC_PWRM_THERMAL_TL_TLLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_PHLC, : .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_TLEN, : .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK, : }, : }; : : for (int i = 0; i < ARRAY_SIZE(config); i++) : config[i].func(pmc_bar + config[i].offset, config[i].value); : } : > just thinking out loud, should this go in src/soc/intel/common/block/pmclib. […] That could work, if this will be part of PMC in the future. But we never what will be in next or next next generation. Maybe move out PMC. I vote keep this in thermal for better maintenance. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 03:29:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Modified `pch_get_ltt_value()` return type
by EricR Lai (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59311 ) Change subject: soc/intel/../thermal: Modified `pch_get_ltt_value()` return type ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Just curious, why need change to int32? PCH register enlarge to DWORD? -- To view, visit https://review.coreboot.org/c/coreboot/+/59311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f46ccb457b9cfebf13a512eabb3fb0fab8adb39 Gerrit-Change-Number: 59311 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 03:26:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021