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Change in coreboot[master]: soc/mediatek/mt8186: Add mtcmos init support
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59343 ) Change subject: soc/mediatek/mt8186: Add mtcmos init support ...................................................................... soc/mediatek/mt8186: Add mtcmos init support Add mtcmos to support display and audio. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen(a)mediatek.com> Change-Id: Ib9d41d47f235376f524c3ff78f1fcc069cbc60cd --- M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/spm.h A src/soc/mediatek/mt8186/mtcmos.c M src/soc/mediatek/mt8186/spm.c 4 files changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/59343/1 diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 92f7e6a..35f9873 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index c60d62b..18a9744 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -10,6 +10,7 @@ #include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/mtcmos.h> #include <types.h> #define SPM_INIT_DONE_US 20 @@ -140,7 +141,7 @@ PCM_SW_INT0) struct mtk_spm_regs { - uint32_t poweron_config_en; + uint32_t poweron_config_set; uint32_t spm_power_on_val0; uint32_t spm_power_on_val1; uint32_t spm_clk_con; @@ -833,6 +834,8 @@ /* Auto-gen End */ }; +check_member(mtk_spm_regs, poweron_config_set, 0x0); +check_member(mtk_spm_regs, dis_pwr_con, 0x354); check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); @@ -853,6 +856,19 @@ static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = 0x1 << 21, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, +}; + +/* without audio mtcmos control in MT8186 */ +static const struct power_domain_data audio[] = { +}; + int spm_init(void); #endif /* SOC_MEDIATEK_MT8186_SPM_H */ diff --git a/src/soc/mediatek/mt8186/mtcmos.c b/src/soc/mediatek/mt8186/mtcmos.c new file mode 100644 index 0000000..314edd5 --- /dev/null +++ b/src/soc/mediatek/mt8186/mtcmos.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/mtcmos.h> + +enum { + DISP_PROT_STEP_2_MASK = 0x00000C06, + DISP_PROT_STEP_1_MASK = 0x00001800, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8186_infracfg_ao->infra_topaxi_protecten_clr, + DISP_PROT_STEP_2_MASK); + write32(&mt8186_infracfg_ao->infra_topaxi_protecten_1_clr, + DISP_PROT_STEP_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + /* No need to do protection since MT8186 doesn't have audio mtcmos. */ +} diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c index 41fa913..bc263eb 100644 --- a/src/soc/mediatek/mt8186/spm.c +++ b/src/soc/mediatek/mt8186/spm.c @@ -384,7 +384,7 @@ static void spm_register_init(void) { /* Enable register control */ - write32(&mtk_spm->poweron_config_en, + write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); /* Init power control register */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9d41d47f235376f524c3ff78f1fcc069cbc60cd Gerrit-Change-Number: 59343 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Chun-Jie Chen <chun-jie.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/corsola: Initialize SPM
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59342 ) Change subject: mb/google/corsola: Initialize SPM ...................................................................... mb/google/corsola: Initialize SPM This patch adds support for SPM. This adds 55ms to the boot time. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I822417f7a679107760b202dd43fb79d1934940bd --- M src/mainboard/google/corsola/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/59342/1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 75b8bb5..2ea81e8 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> #include <soc/msdc.h> +#include <soc/spm.h> #include <soc/usb.h> static void mainboard_init(struct device *dev) @@ -9,6 +11,9 @@ mtk_msdc_configure_emmc(true); mtk_msdc_configure_sdcard(); setup_usb_host(); + + if (spm_init()) + printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/59342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I822417f7a679107760b202dd43fb79d1934940bd Gerrit-Change-Number: 59342 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: add SPM loader
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59341 ) Change subject: soc/mediatek/mt8186: add SPM loader ...................................................................... soc/mediatek/mt8186: add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 --- M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/spm.h A src/soc/mediatek/mt8186/spm.c 4 files changed, 1,019 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/59341/1 diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index dc3f9bb..ce915e2 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -16,6 +16,12 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE +config SPM_FIRMWARE + string + default "spm_firmware.bin" + help + The file name of the MediaTek SPM firmware. + config SSPM_FIRMWARE string default "sspm.bin" diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 00b12e8..92f7e6a 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -46,6 +46,7 @@ ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c +ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c @@ -59,7 +60,8 @@ MT8186_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8186 mcu-firmware-files := \ - $(CONFIG_SSPM_FIRMWARE) + $(CONFIG_SSPM_FIRMWARE) \ + $(CONFIG_SPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8186_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index 5ab11ea..c60d62b 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -8,9 +8,137 @@ #ifndef SOC_MEDIATEK_MT8186_SPM_H #define SOC_MEDIATEK_MT8186_SPM_H +#include <device/mmio.h> #include <soc/addressmap.h> #include <types.h> +#define SPM_INIT_DONE_US 20 + +#define CLK_SCP_CFG_0 (IO_PHYS + 0x200) +#define CLK_SCP_CFG_1 (IO_PHYS + 0x210) +#define INFRA_AO_RES_CTRL_MASK (INFRACFG_AO_BASE + 0xB8) + +#define AP_PLL_CON3 (APMIXED_BASE + 0xC) +#define AP_PLL_CON4 (APMIXED_BASE + 0x10) + +/* MD32PCM ADDR for SPM code fetch */ +#define MD32PCM_BASE (SPM_BASE + 0x0A00) +#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000) +#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200) +#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204) +#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208) +#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C) +#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210) +#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214) +#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218) +#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224) +#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C) + +#define MD32PCM_CFGREG_SW_RSTN_RUN 1 +#define MD32PCM_DMA0_CON_VAL 0x0003820E +#define MD32PCM_DMA0_START_VAL 0x00008000 + +/* SPM */ +#define BCLK_CG_EN_LSB BIT(0) +#define PCM_CK_EN_LSB BIT(2) +#define PCM_SW_RESET_LSB BIT(15) +#define RG_AHBMIF_APBEN_LSB BIT(3) +#define REG_MD32_APB_INTERNAL_EN_LSB BIT(14) +#define PCM_RF_SYNC_R7 BIT(23) +#define REG_DDREN_DBC_EN_LSB BIT(16) + +DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) +DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28) +DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1) +DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4) +DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8) +DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 9) +DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 10) +DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 18) +DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 15) +DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2) +DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4) +DEFINE_BIT(SYS_TIMER_START_EN_LSB, 0) + +#define SPM_PROJECT_CODE 0xB16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) +#define POWER_ON_VAL1_DEF 0x80015860 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xEFFFFFFF +#define DDREN_DBC_EN_VAL 0x154 +#define ARMPLL_CLK_SEL_DEF 0x3FF +#define SPM_RESOURCE_ACK_CON0_DEF 0x00000000 +#define SPM_RESOURCE_ACK_CON1_DEF 0x00000000 +#define SPM_RESOURCE_ACK_CON2_DEF 0xCCCC4E4E +#define SPM_RESOURCE_ACK_CON3_DEF 0x00000000 +#define APMIX_CON3_DEF 0xFFFF7770 +#define APMIX_CON4_DEF 0xFFFAA007 +#define SCP_CFG0_DEF 0x3FF +#define SCP_CFG1_DEF 0x3 +#define SPM_DVFS_LEVEL_DEF 0x00000001 +#define SPM_DVS_DFS_LEVEL_DEF 0x00010001 +#define SPM_ACK_CHK_3_SEL_HW_S1 0x0035009F +#define SPM_ACK_CHK_3_HW_S1_CNT 1 +#define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */ +#define SPM_WAKEUP_EVENT_MASK_BIT0 1 +#define RG_PCM_TIMER_EN_LSB BIT(5) +#define RG_PCM_WDT_WAKE_LSB BIT(9) +#define PCM_RF_SYNC_R0 BIT(16) +#define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(6) +#define R12_CSYSPWREQ_B BIT(24) +#define SPM_BUS_PROTECT_MASK_B_DEF 0xFFFFFFFF +#define SPM_BUS_PROTECT2_MASK_B_DEF 0xFFFFFFFF + +#define SPM_FLAG_DISABLE_VCORE_DVS BIT(3) +#define SPM_FLAG_DISABLE_VCORE_DFS BIT(4) +#define SPM_FLAG_RUN_COMMON_SCENARIO BIT(10) + +/* PCM_WDT_VAL */ +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +/* PCM_TIMER_VAL */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/* SPM_IRQ_MASK */ +#define ISRM_TWAM BIT(2) +#define ISRM_PCM_RETURN BIT(3) +#define ISRM_RET_IRQ0 BIT(8) +#define ISRM_RET_IRQ1 BIT(9) +#define ISRM_RET_IRQ2 BIT(10) +#define ISRM_RET_IRQ3 BIT(11) +#define ISRM_RET_IRQ4 BIT(12) +#define ISRM_RET_IRQ5 BIT(13) +#define ISRM_RET_IRQ6 BIT(14) +#define ISRM_RET_IRQ7 BIT(15) +#define ISRM_RET_IRQ8 BIT(16) +#define ISRM_RET_IRQ9 BIT(17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | ISRM_RET_IRQ7 | \ + ISRM_RET_IRQ6 | ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | ISRM_RET_IRQ1) +#define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM BIT(2) +#define ISRS_PCM_RETURN BIT(3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_SWINT */ +#define PCM_SW_INT0 BIT(0) +#define PCM_SW_INT1 BIT(1) +#define PCM_SW_INT2 BIT(2) +#define PCM_SW_INT3 BIT(3) +#define PCM_SW_INT4 BIT(4) +#define PCM_SW_INT5 BIT(5) +#define PCM_SW_INT6 BIT(6) +#define PCM_SW_INT7 BIT(7) +#define PCM_SW_INT8 BIT(8) +#define PCM_SW_INT9 BIT(9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) + struct mtk_spm_regs { uint32_t poweron_config_en; uint32_t spm_power_on_val0; @@ -522,12 +650,209 @@ uint32_t adsp_ao_pwr_con; }; +struct pwr_ctrl { + /* For SPM */ + uint32_t pcm_flags; + uint32_t pcm_flags_cust; + uint32_t pcm_flags_cust_set; + uint32_t pcm_flags_cust_clr; + uint32_t pcm_flags1; + uint32_t pcm_flags1_cust; + uint32_t pcm_flags1_cust_set; + uint32_t pcm_flags1_cust_clr; + uint32_t timer_val; + uint32_t timer_val_cust; + uint32_t timer_val_ramp_en; + uint32_t timer_val_ramp_en_sec; + uint32_t wake_src; + uint32_t wake_src_cust; + uint32_t wakelock_timer_val; + uint8_t wdt_disable; + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + uint8_t reg_wfi_op; + uint8_t reg_wfi_type; + uint8_t reg_mp0_cputop_idle_mask; + uint8_t reg_mp1_cputop_idle_mask; + uint8_t reg_mcusys_idle_mask; + uint8_t reg_md_apsrc_1_sel; + uint8_t reg_md_apsrc_0_sel; + uint8_t reg_conn_apsrc_sel; + + /* SPM_SRC6_MASK */ + uint32_t reg_ccif_event_infra_req_mask_b; + uint32_t reg_ccif_event_apsrc_req_mask_b; + + /* SPM_SRC_REQ */ + uint8_t reg_spm_apsrc_req; + uint8_t reg_spm_f26m_req; + uint8_t reg_spm_infra_req; + uint8_t reg_spm_vrf18_req; + uint8_t reg_spm_ddren_req; + uint8_t reg_spm_dvfs_req; + uint8_t reg_spm_sw_mailbox_req; + uint8_t reg_spm_sspm_mailbox_req; + uint8_t reg_spm_adsp_mailbox_req; + uint8_t reg_spm_scp_mailbox_req; + + /* SPM_SRC_MASK */ + uint8_t reg_md_0_srcclkena_mask_b; + uint8_t reg_md_0_infra_req_mask_b; + uint8_t reg_md_0_apsrc_req_mask_b; + uint8_t reg_md_0_vrf18_req_mask_b; + uint8_t reg_md_0_ddren_req_mask_b; + uint8_t reg_md_1_srcclkena_mask_b; + uint8_t reg_md_1_infra_req_mask_b; + uint8_t reg_md_1_apsrc_req_mask_b; + uint8_t reg_md_1_vrf18_req_mask_b; + uint8_t reg_md_1_ddren_req_mask_b; + uint8_t reg_conn_srcclkena_mask_b; + uint8_t reg_conn_srcclkenb_mask_b; + uint8_t reg_conn_infra_req_mask_b; + uint8_t reg_conn_apsrc_req_mask_b; + uint8_t reg_conn_vrf18_req_mask_b; + uint8_t reg_conn_ddren_req_mask_b; + uint8_t reg_conn_vfe28_mask_b; + uint8_t reg_srcclkeni_srcclkena_mask_b; + uint8_t reg_srcclkeni_infra_req_mask_b; + uint8_t reg_infrasys_apsrc_req_mask_b; + uint8_t reg_infrasys_ddren_req_mask_b; + uint8_t reg_sspm_srcclkena_mask_b; + uint8_t reg_sspm_infra_req_mask_b; + uint8_t reg_sspm_apsrc_req_mask_b; + uint8_t reg_sspm_vrf18_req_mask_b; + uint8_t reg_sspm_ddren_req_mask_b; + + /* SPM_SRC2_MASK */ + uint8_t reg_scp_srcclkena_mask_b; + uint8_t reg_scp_infra_req_mask_b; + uint8_t reg_scp_apsrc_req_mask_b; + uint8_t reg_scp_vrf18_req_mask_b; + uint8_t reg_scp_ddren_req_mask_b; + uint8_t reg_audio_dsp_srcclkena_mask_b; + uint8_t reg_audio_dsp_infra_req_mask_b; + uint8_t reg_audio_dsp_apsrc_req_mask_b; + uint8_t reg_audio_dsp_vrf18_req_mask_b; + uint8_t reg_audio_dsp_ddren_req_mask_b; + uint8_t reg_ufs_srcclkena_mask_b; + uint8_t reg_ufs_infra_req_mask_b; + uint8_t reg_ufs_apsrc_req_mask_b; + uint8_t reg_ufs_vrf18_req_mask_b; + uint8_t reg_ufs_ddren_req_mask_b; + uint8_t reg_disp0_apsrc_req_mask_b; + uint8_t reg_disp0_ddren_req_mask_b; + uint8_t reg_disp1_apsrc_req_mask_b; + uint8_t reg_disp1_ddren_req_mask_b; + uint8_t reg_gce_infra_req_mask_b; + uint8_t reg_gce_apsrc_req_mask_b; + uint8_t reg_gce_vrf18_req_mask_b; + uint8_t reg_gce_ddren_req_mask_b; + uint8_t reg_apu_srcclkena_mask_b; + uint8_t reg_apu_infra_req_mask_b; + uint8_t reg_apu_apsrc_req_mask_b; + uint8_t reg_apu_vrf18_req_mask_b; + uint8_t reg_apu_ddren_req_mask_b; + uint8_t reg_cg_check_srcclkena_mask_b; + uint8_t reg_cg_check_apsrc_req_mask_b; + uint8_t reg_cg_check_vrf18_req_mask_b; + uint8_t reg_cg_check_ddren_req_mask_b; + + /* SPM_SRC3_MASK */ + uint8_t reg_dvfsrc_event_trigger_mask_b; + uint8_t reg_sw2spm_wakeup_mask_b; + uint8_t reg_adsp2spm_wakeup_mask_b; + uint8_t reg_sspm2spm_wakeup_mask_b; + uint8_t reg_scp2spm_wakeup_mask_b; + uint8_t reg_csyspwrup_ack_mask; + uint8_t reg_spm_reserved_srcclkena_mask_b; + uint8_t reg_spm_reserved_infra_req_mask_b; + uint8_t reg_spm_reserved_apsrc_req_mask_b; + uint8_t reg_spm_reserved_vrf18_req_mask_b; + uint8_t reg_spm_reserved_ddren_req_mask_b; + uint8_t reg_mcupm_srcclkena_mask_b; + uint8_t reg_mcupm_infra_req_mask_b; + uint8_t reg_mcupm_apsrc_req_mask_b; + uint8_t reg_mcupm_vrf18_req_mask_b; + uint8_t reg_mcupm_ddren_req_mask_b; + uint8_t reg_msdc0_srcclkena_mask_b; + uint8_t reg_msdc0_infra_req_mask_b; + uint8_t reg_msdc0_apsrc_req_mask_b; + uint8_t reg_msdc0_vrf18_req_mask_b; + uint8_t reg_msdc0_ddren_req_mask_b; + uint8_t reg_msdc1_srcclkena_mask_b; + uint8_t reg_msdc1_infra_req_mask_b; + uint8_t reg_msdc1_apsrc_req_mask_b; + uint8_t reg_msdc1_vrf18_req_mask_b; + uint8_t reg_msdc1_ddren_req_mask_b; + + /* SPM_SRC4_MASK */ + uint32_t reg_ccif_event_srcclkena_mask_b; + uint8_t reg_bak_psri_srcclkena_mask_b; + uint8_t reg_bak_psri_infra_req_mask_b; + uint8_t reg_bak_psri_apsrc_req_mask_b; + uint8_t reg_bak_psri_vrf18_req_mask_b; + uint8_t reg_bak_psri_ddren_req_mask_b; + uint8_t reg_dramc_md32_infra_req_mask_b; + uint8_t reg_dramc_md32_vrf18_req_mask_b; + uint8_t reg_conn_srcclkenb2pwrap_mask_b; + uint8_t reg_dramc_md32_apsrc_req_mask_b; + + /* SPM_SRC5_MASK */ + uint32_t reg_mcusys_merge_apsrc_req_mask_b; + uint32_t reg_mcusys_merge_ddren_req_mask_b; + uint8_t reg_afe_srcclkena_mask_b; + uint8_t reg_afe_infra_req_mask_b; + uint8_t reg_afe_apsrc_req_mask_b; + uint8_t reg_afe_vrf18_req_mask_b; + uint8_t reg_afe_ddren_req_mask_b; + uint8_t reg_msdc2_srcclkena_mask_b; + uint8_t reg_msdc2_infra_req_mask_b; + uint8_t reg_msdc2_apsrc_req_mask_b; + uint8_t reg_msdc2_vrf18_req_mask_b; + uint8_t reg_msdc2_ddren_req_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + uint32_t reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + uint32_t reg_ext_wakeup_event_mask; + + /* SPM_SRC7_MASK */ + uint8_t reg_pcie_srcclkena_mask_b; + uint8_t reg_pcie_infra_req_mask_b; + uint8_t reg_pcie_apsrc_req_mask_b; + uint8_t reg_pcie_vrf18_req_mask_b; + uint8_t reg_pcie_ddren_req_mask_b; + uint8_t reg_dpmaif_srcclkena_mask_b; + uint8_t reg_dpmaif_infra_req_mask_b; + uint8_t reg_dpmaif_apsrc_req_mask_b; + uint8_t reg_dpmaif_vrf18_req_mask_b; + uint8_t reg_dpmaif_ddren_req_mask_b; + + /* Auto-gen End */ +}; + check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8); check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC); +struct pcm_desc { + uint32_t pmem_words; + uint32_t total_words; + uint32_t pmem_start; + uint32_t dmem_start; +}; + +struct dyna_load_pcm { + u8 *buf; /* binary array */ + struct pcm_desc desc; +}; + static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +int spm_init(void); + #endif /* SOC_MEDIATEK_MT8186_SPM_H */ diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c new file mode 100644 index 0000000..41fa913 --- /dev/null +++ b/src/soc/mediatek/mt8186/spm.c @@ -0,0 +1,685 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.5 + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mcu_common.h> +#include <soc/spm.h> +#include <soc/spm_common.h> +#include <soc/symbols.h> +#include <string.h> +#include <timer.h> + +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + +static const struct pwr_ctrl spm_init_ctrl = { + /* For SPM, this flag is not auto-gen. */ + .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | + SPM_FLAG_DISABLE_VCORE_DFS | + SPM_FLAG_RUN_COMMON_SCENARIO, + + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_ccif_event_infra_req_mask_b = 0xFFFF, + .reg_ccif_event_apsrc_req_mask_b = 0xFFFF, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_vrf18_req = 0, + .reg_spm_ddren_req = 0, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_0_srcclkena_mask_b = 1, + .reg_md_0_infra_req_mask_b = 1, + .reg_md_0_apsrc_req_mask_b = 1, + .reg_md_0_vrf18_req_mask_b = 1, + .reg_md_0_ddren_req_mask_b = 1, + .reg_md_1_srcclkena_mask_b = 0, + .reg_md_1_infra_req_mask_b = 0, + .reg_md_1_apsrc_req_mask_b = 0, + .reg_md_1_vrf18_req_mask_b = 0, + .reg_md_1_ddren_req_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddren_req_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni_srcclkena_mask_b = 1, + .reg_srcclkeni_infra_req_mask_b = 1, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddren_req_mask_b = 1, + .reg_sspm_srcclkena_mask_b = 1, + .reg_sspm_infra_req_mask_b = 1, + .reg_sspm_apsrc_req_mask_b = 1, + .reg_sspm_vrf18_req_mask_b = 1, + .reg_sspm_ddren_req_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddren_req_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddren_req_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddren_req_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddren_req_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddren_req_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddren_req_mask_b = 1, + .reg_apu_srcclkena_mask_b = 0, + .reg_apu_infra_req_mask_b = 0, + .reg_apu_apsrc_req_mask_b = 0, + .reg_apu_vrf18_req_mask_b = 0, + .reg_apu_ddren_req_mask_b = 0, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddren_req_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_wakeup_mask_b = 0, + .reg_adsp2spm_wakeup_mask_b = 0, + .reg_sspm2spm_wakeup_mask_b = 0, + .reg_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrup_ack_mask = 1, + .reg_spm_reserved_srcclkena_mask_b = 0, + .reg_spm_reserved_infra_req_mask_b = 0, + .reg_spm_reserved_apsrc_req_mask_b = 0, + .reg_spm_reserved_vrf18_req_mask_b = 0, + .reg_spm_reserved_ddren_req_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddren_req_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddren_req_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddren_req_mask_b = 1, + + /* SPM_SRC4_MASK */ + .reg_ccif_event_srcclkena_mask_b = 0x3FF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddren_req_mask_b = 0, + .reg_dramc_md32_infra_req_mask_b = 1, + .reg_dramc_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc_md32_apsrc_req_mask_b = 0, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x14, + .reg_mcusys_merge_ddren_req_mask_b = 0x14, + .reg_afe_srcclkena_mask_b = 0, + .reg_afe_infra_req_mask_b = 0, + .reg_afe_apsrc_req_mask_b = 0, + .reg_afe_vrf18_req_mask_b = 0, + .reg_afe_ddren_req_mask_b = 0, + .reg_msdc2_srcclkena_mask_b = 0, + .reg_msdc2_infra_req_mask_b = 0, + .reg_msdc2_apsrc_req_mask_b = 0, + .reg_msdc2_vrf18_req_mask_b = 0, + .reg_msdc2_ddren_req_mask_b = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFFF, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* SPM_SRC7_MASK */ + .reg_pcie_srcclkena_mask_b = 0, + .reg_pcie_infra_req_mask_b = 0, + .reg_pcie_apsrc_req_mask_b = 0, + .reg_pcie_vrf18_req_mask_b = 0, + .reg_pcie_ddren_req_mask_b = 0, + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddren_req_mask_b = 1, + + /* Auto-gen End */ +}; + +static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + write32(&mtk_spm->spm_ap_standby_con, + ((pwrctrl->reg_wfi_op & 0x1) << 0) | + ((pwrctrl->reg_wfi_type & 0x1) << 1) | + ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | + ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); + + /* SPM_SRC6_MASK */ + write32(&mtk_spm->spm_src6_mask, + ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16)); + + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); + + /* SPM_SRC_MASK */ + write32(&mtk_spm->spm_src_mask, + ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) | + ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) | + ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC2_MASK */ + write32(&mtk_spm->spm_src2_mask, + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC3_MASK */ + write32(&mtk_spm->spm_src3_mask, + ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | + ((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) | + ((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) | + ((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) | + ((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) | + ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) | + ((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC4_MASK */ + write32(&mtk_spm->spm_src4_mask, + ((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | + ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) | + ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) | + ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | + ((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26)); + + /* SPM_SRC5_MASK */ + write32(&mtk_spm->spm_src5_mask, + ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | + ((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) | + ((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) | + ((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_SRC7_MASK */ + write32(&mtk_spm->spm_src7_mask, + ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9)); + /* Auto-gen End */ +} + +static void spm_hw_s1_state_monitor(int en) +{ + if (en) + SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3, + SPM_ACK_CHK_3_CON_CLR_ALL, 0, + SPM_ACK_CHK_3_CON_EN_0, 1, + SPM_ACK_CHK_3_CON_EN_1, 1); + else + SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 1, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 1, + SPM_ACK_CHK_3_CON_CLR_ALL, 1, + SPM_ACK_CHK_3_CON_EN_0, 0, + SPM_ACK_CHK_3_CON_EN_1, 0); +} + +static void spm_register_init(void) +{ + /* Enable register control */ + write32(&mtk_spm->poweron_config_en, + SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + /* Init power control register */ + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | + REG_MD32_APB_INTERNAL_EN_LSB); + + /* Initial SPM CLK control register */ + SET32_BITFIELDS(&mtk_spm->spm_clk_con, + REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1); + + /* Clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* Clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + /* Init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* DDR EN de-bounce length to 5us */ + write32(&mtk_spm->ddren_dbc_con, DDREN_DBC_EN_VAL | REG_DDREN_DBC_EN_LSB); + + /* Configure ARMPLL Control Mode for MCDI */ + write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF); + + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF); + write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF); + write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF); + write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); + + /* Enable Side-Band */ + write32((void *)AP_PLL_CON3, APMIX_CON3_DEF); + write32((void *)AP_PLL_CON4, APMIX_CON4_DEF); + write32((void *)CLK_SCP_CFG_0, SCP_CFG0_DEF); + write32((void *)CLK_SCP_CFG_1, SCP_CFG1_DEF); + + /* Init VCORE DVFS Status */ + SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, + SPM_DVFS_FORCE_ENABLE_LSB, 0, + SPM_DVFSRC_ENABLE_LSB, 1); + write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); + write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); + + write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT); + + spm_hw_s1_state_monitor(0); +} + +static void spm_extern_initialize(void) +{ + SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, + INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1, + INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1); +} + +static void spm_set_sysclk_settle(void) +{ + write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE); +} + +static void spm_code_swapping(void) +{ + u32 mask; + + mask = read32(&mtk_spm->spm_wakeup_event_mask); + write32(&mtk_spm->spm_wakeup_event_mask, + mask & ~SPM_WAKEUP_EVENT_MASK_BIT0); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, mask); +} + +static void spm_reset_and_init_pcm(void) +{ + bool first_load_fw = true; + + /* Check whether the SPM FW is running */ + if (read32((void *)MD32PCM_CFGREG_SW_RSTN) & MD32PCM_CFGREG_SW_RSTN_RUN) + first_load_fw = false; + + if (!first_load_fw) { + spm_code_swapping(); + /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */ + write32(&mtk_spm->spm_power_on_val0, + read32(&mtk_spm->pcm_reg0_data)); + } + + /* Disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Disable pcm timer after leaving FW */ + clrsetbits32(&mtk_spm->pcm_con1, + RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); + + /* Reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB, + SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); +} + +static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) +{ + uintptr_t ptr; + u32 dmem_words; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; + + ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; + pmem_words = pcm->desc.pmem_words; + total_words = pcm->desc.total_words; + dmem_words = total_words - pmem_words; + pmem_start = pcm->desc.pmem_start; + dmem_start = pcm->desc.dmem_start; + + printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", + __func__, (long)ptr, pmem_words, dmem_words); + + /* DMA needs 16-byte aligned source data. */ + assert(ptr % 16 == 0); + + write32((void *)MD32PCM_DMA0_SRC, ptr); + write32((void *)MD32PCM_DMA0_DST, pmem_start); + write32((void *)MD32PCM_DMA0_WPPT, pmem_words); + write32((void *)MD32PCM_DMA0_WPTO, dmem_start); + write32((void *)MD32PCM_DMA0_COUNT, total_words); + write32((void *)MD32PCM_DMA0_CON, MD32PCM_DMA0_CON_VAL); + write32((void *)MD32PCM_DMA0_START, MD32PCM_DMA0_START_VAL); + + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + /* Init r0 with POWER_ON_VAL0 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + u32 val, mask; + + /* Toggle event counter clear */ + setbits32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB); + + /* Toggle for reset SYS TIMER start point */ + SET32_BITFIELDS(&mtk_spm->sys_timer_con, + SYS_TIMER_START_EN_LSB, 1); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + + setbits32(&mtk_spm->pcm_con1, RG_PCM_TIMER_EN_LSB | SPM_REGWR_CFG_KEY); + + /* Unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrup_ack_mask) + mask &= ~R12_CSYSPWREQ_B; + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* Unmask SPM ISR */ + setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX); + + /* Toggle event counter clear */ + clrsetbits32(&mtk_spm->pcm_con1, REG_SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); + + /* Toggle for reset SYS TIMER start point */ + SET32_BITFIELDS(&mtk_spm->sys_timer_con, + SYS_TIMER_START_EN_LSB, 0); +} + +static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +{ + u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; + + /* Set PCM flags and data */ + if (pwrctrl->pcm_flags_cust_clr != 0) + pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; + if (pwrctrl->pcm_flags_cust_set != 0) + pcm_flags |= pwrctrl->pcm_flags_cust_set; + if (pwrctrl->pcm_flags1_cust_clr != 0) + pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; + if (pwrctrl->pcm_flags1_cust_set != 0) + pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; + + write32(&mtk_spm->spm_sw_flag_0, pcm_flags); + write32(&mtk_spm->spm_sw_flag_1, pcm_flags1); + write32(&mtk_spm->spm_sw_rsv_7, pcm_flags); + write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); +} + +static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) +{ + /* Waiting for loading SPMFW done*/ + while (read32((void *)MD32PCM_DMA0_RLCT) != 0x0) + ; + + /* Init register to match PCM expectation */ + write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); + write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + SET32_BITFIELDS((void *)MD32PCM_CFGREG_SW_RSTN, + MD32PCM_CFGREG_SW_RSTN_RESET, 1); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} + +static void reset_spm(struct mtk_mcu *mcu) +{ + struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv; + + spm_parse_firmware(mcu); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcm); + spm_init_pcm_register(); + spm_set_power_control(&spm_init_ctrl); + spm_set_wakeup_event(&spm_init_ctrl); + spm_kick_pcm_to_run(&spm_init_ctrl); +} + +static struct mtk_mcu spm = { + .firmware_name = CONFIG_SPM_FIRMWARE, + .reset = reset_spm, +}; + +int spm_init(void) +{ + struct dyna_load_pcm pcm; + struct stopwatch sw; + + stopwatch_init(&sw); + + spm_register_init(); + spm_set_power_control(&spm_init_ctrl); + spm_set_sysclk_settle(); + spm_extern_initialize(); + + spm.load_buffer = _dram_dma; + spm.buffer_size = REGION_SIZE(dram_dma); + spm.priv = (void *)&pcm; + + if (mtk_init_mcu(&spm)) { + printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__); + return -1; + } + + printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n", + __func__, stopwatch_duration_msecs(&sw), + read32(&mtk_spm->md32pcm_pc)); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 Gerrit-Change-Number: 59341 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: initialize sspm
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59340 ) Change subject: soc/mediatek/mt8186: initialize sspm ...................................................................... soc/mediatek/mt8186: initialize sspm Add drivers of loading sspm.bin. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391 --- M src/soc/mediatek/mt8186/Kconfig M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/addressmap.h M src/soc/mediatek/mt8186/soc.c 4 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/59340/1 diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index 9b8708a..dc3f9bb 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -16,6 +16,12 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE +config SSPM_FIRMWARE + string + default "sspm.bin" + help + The file name of the MediaTek SSPM firmware. + config FLASH_DUAL_READ bool default y diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 0646f6c..00b12e8 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -41,10 +41,12 @@ ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/i2c.c i2c.c +ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c @@ -54,6 +56,18 @@ CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +MT8186_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8186 + +mcu-firmware-files := \ + $(CONFIG_SSPM_FIRMWARE) + +$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ + $(eval $(fw)-file := $(MT8186_BLOB_DIR)/$(fw)) \ + $(eval $(fw)-type := raw) \ + $(eval $(fw)-compression := LZ4) \ + $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ +) + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index cabafb6..6a5ce5c 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -45,6 +45,8 @@ EMI0_BASE = IO_PHYS + 0x00219000, EMI0_MPU_BASE = IO_PHYS + 0x0021B000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, SFLASH_REG_BASE = IO_PHYS + 0x01000000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c index dcb9703..e20b447 100644 --- a/src/soc/mediatek/mt8186/soc.c +++ b/src/soc/mediatek/mt8186/soc.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -13,6 +14,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + sspm_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/59340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391 Gerrit-Change-Number: 59340 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek: move MSDC drivers to soc folder
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59339 ) Change subject: soc/mediatek: move MSDC drivers to soc folder ...................................................................... soc/mediatek: move MSDC drivers to soc folder Setting of MSDC is defined by soc, so we move them to soc folder. TEST=emerge-cherry coreboot; emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d --- M src/mainboard/google/asurada/mainboard.c M src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/msdc.c M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/msdc.c 6 files changed, 204 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/59339/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 7704899f..bbca4b8 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -142,72 +142,6 @@ return true; } -static void configure_emmc(void) -{ - void *gpio_base = (void *)IOCFG_TL_BASE; - int i; - - const gpio_t emmc_pu_pin[] = { - GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), - GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), - GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), - GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), - GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), - }; - - const gpio_t emmc_pd_pin[] = { - GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) - gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) - gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ - clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); - - mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); -} - -static void configure_sdcard(void) -{ - void *gpio_base = (void *)IOCFG_RM_BASE; - void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; - void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; - uint8_t enable = 1; - int i; - - const gpio_t sdcard_pu_pin[] = { - GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), - GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), - GPIO(MSDC1_CMD), - }; - - const gpio_t sdcard_pd_pin[] = { - GPIO(MSDC1_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) - gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) - gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set sdcard cmd/dat/clk pins driving to 8mA */ - clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); - - /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ - clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); - - /* set sdcard dat1 pin to msdc1 mode */ - clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); - - mainboard_enable_regulator(MTK_REGULATOR_VCC, enable); - mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); -} - static void configure_audio(void) { /* Audio PWR */ @@ -222,8 +156,8 @@ static void mainboard_init(struct device *dev) { - configure_emmc(); - configure_sdcard(); + mtk_msdc_configure_emmc(true); + mtk_msdc_configure_sdcard(); configure_audio(); setup_usb_host(); diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index a097050..92d8ee1 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -15,9 +15,7 @@ #include <soc/gpio.h> #include <soc/i2c.h> #include <soc/msdc.h> -#include <soc/mt6360.h> #include <soc/mtcmos.h> -#include <soc/regulator.h> #include <soc/spm.h> #include <soc/usb.h> @@ -31,28 +29,6 @@ #define GPIO_EDP_HPD_1V8 GPIO(GPIO_07) #define GPIO_EN_PP3300_DISP_X GPIO(I2SO1_D2) -DEFINE_BITFIELD(MSDC0_DRV, 29, 0) -DEFINE_BITFIELD(MSDC1_DRV, 17, 0) -DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) -DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) - -#define MSDC0_BASE 0x11230000 -#define MSDC0_TOP_BASE 0x11f50000 - -#define MSDC0_DRV_VALUE 0x1b6db6db -#define MSDC1_DRV_VALUE 0x1b6db -#define MSDC1_GPIO_MODE0_VALUE 0x1 -#define MSDC1_GPIO_MODE1_VALUE 0x1 - -enum { - MSDC1_GPIO_MODE0_BASE = 0x100053d0, - MSDC1_GPIO_MODE1_BASE = 0x100053e0, -}; - static void register_reset_to_bl31(void) { static struct bl_aux_param_gpio param_reset = { @@ -64,82 +40,6 @@ register_bl31_aux_param(&param_reset.h); } -static void configure_emmc(void) -{ - void *gpio_base = (void *)IOCFG_TL_BASE; - int i; - - const gpio_t emmc_pu_pin[] = { - GPIO(EMMC_DAT0), GPIO(EMMC_DAT1), - GPIO(EMMC_DAT2), GPIO(EMMC_DAT3), - GPIO(EMMC_DAT4), GPIO(EMMC_DAT5), - GPIO(EMMC_DAT6), GPIO(EMMC_DAT7), - GPIO(EMMC_CMD), GPIO(EMMC_RSTB), - }; - - const gpio_t emmc_pd_pin[] = { - GPIO(EMMC_DSL), GPIO(EMMC_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) - gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) - gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ - SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); - - mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); -} - -static void configure_sdcard(void) -{ - void *gpio_base = (void *)IOCFG_RB_BASE; - void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; - void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; - int i; - - const gpio_t sdcard_pu_pin[] = { - GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), - GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), - GPIO(MSDC1_CMD), - }; - - const gpio_t sdcard_pd_pin[] = { - GPIO(MSDC1_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) - gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) - gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set sdcard cmd/dat/clk pins driving to 8mA */ - SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); - - /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ - SET32_BITFIELDS(gpio_mode0_base, - MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, - MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); - - /* set sdcard dat1 pin to msdc1 mode */ - SET32_BITFIELDS(gpio_mode1_base, - MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, - MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, - MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, - MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); - - mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST); - - if (CONFIG(BOARD_GOOGLE_CHERRY)) - mt6360_init(I2C7); - - mainboard_enable_regulator(MTK_REGULATOR_VCCQ, 1); - mainboard_enable_regulator(MTK_REGULATOR_VCC, 1); -} - /* Set up backlight control pins as output pin and power-off by default */ static void configure_panel_backlight(void) { @@ -199,8 +99,8 @@ else printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); - configure_emmc(); - configure_sdcard(); + mtk_msdc_configure_emmc(true); + mtk_msdc_configure_sdcard(); setup_usb_host(); /* for audio usage */ diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e5ca485..a75ac28 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -56,7 +56,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c -ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c diff --git a/src/soc/mediatek/mt8192/msdc.c b/src/soc/mediatek/mt8192/msdc.c new file mode 100644 index 0000000..113069a --- /dev/null +++ b/src/soc/mediatek/mt8192/msdc.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/regulator.h> +#include <soc/msdc.h> + +#define MSDC0_BASE 0x11f60000 +#define MSDC0_TOP_BASE 0x11f50000 + +#define MSDC0_DRV_MASK 0x3fffffff +#define MSDC1_DRV_MASK 0x3ffff000 +#define MSDC0_DRV_VALUE 0x24924924 +#define MSDC1_DRV_VALUE 0x1b6db000 + +#define MSDC1_GPIO_MODE0_BASE 0x10005360 +#define MSDC1_GPIO_MODE0_MASK 0x77777000 +#define MSDC1_GPIO_MODE0_VALUE 0x11111000 + +#define MSDC1_GPIO_MODE1_BASE 0x10005370 +#define MSDC1_GPIO_MODE1_MASK 0x7 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +void mtk_msdc_configure_emmc(bool is_early_init) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ + clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); + + if (is_early_init) + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RM_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + uint8_t enable = 1; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); + + mainboard_enable_regulator(MTK_REGULATOR_VCC, enable); + mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); +} diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index b22acf9..c6f4226 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -68,7 +68,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c -ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/pll.c pll.c ramstage-y += ../common/pmif.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c diff --git a/src/soc/mediatek/mt8195/msdc.c b/src/soc/mediatek/mt8195/msdc.c new file mode 100644 index 0000000..bbfeaa6 --- /dev/null +++ b/src/soc/mediatek/mt8195/msdc.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/i2c.h> +#include <soc/regulator.h> +#include <soc/msdc.h> +#include <soc/mt6360.h> + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 17, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) + +#define MSDC0_BASE 0x11230000 +#define MSDC0_TOP_BASE 0x11f50000 + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053d0, + MSDC1_GPIO_MODE1_BASE = 0x100053e0, +}; + +void mtk_msdc_configure_emmc(bool is_early_init) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(EMMC_DAT0), GPIO(EMMC_DAT1), + GPIO(EMMC_DAT2), GPIO(EMMC_DAT3), + GPIO(EMMC_DAT4), GPIO(EMMC_DAT5), + GPIO(EMMC_DAT6), GPIO(EMMC_DAT7), + GPIO(EMMC_CMD), GPIO(EMMC_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(EMMC_DSL), GPIO(EMMC_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); + + if (is_early_init) + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); + + mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST); + + if (CONFIG(BOARD_GOOGLE_CHERRY)) + mt6360_init(I2C7); + + mainboard_enable_regulator(MTK_REGULATOR_VCCQ, 1); + mainboard_enable_regulator(MTK_REGULATOR_VCC, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d Gerrit-Change-Number: 59339 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Enable DCM
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59338 ) Change subject: soc/mediatek/mt8186: Enable DCM ...................................................................... soc/mediatek/mt8186: Enable DCM DCM (dynamic clock management) can dynamically slow down or gate clocks during CPU or bus idle. Enable DCM settings on the MT8186 platform. TEST=build pass and check register ok BUG=b:202871018 Signed-off-by: Edward-JW Yang <edward-jw.yang(a)mediatek.corp-partner.google.com> Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf --- M src/soc/mediatek/mt8186/include/soc/pll.h M src/soc/mediatek/mt8186/pll.c 2 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59338/1 diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h index 4638f50a..c744754 100644 --- a/src/soc/mediatek/mt8186/include/soc/pll.h +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -507,4 +507,61 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) DEFINE_BITFIELD(CLK26CALI_0_ENABLE, 12, 12) DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) + +enum { + INFRACFG_AO_AUDIO_BUS_REG0_MASK = (0x1 << 29), + INFRACFG_AO_AUDIO_BUS_REG0_ON = (0x1 << 29), + INFRACFG_AO_ICUSB_BUS_REG0_MASK = (0x1 << 28), + INFRACFG_AO_ICUSB_BUS_REG0_ON = (0x1 << 28), + INFRACFG_AO_INFRA_BUS_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 2) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 10) | + (0x1 << 20) | + (0x1 << 21) | + (0x1 << 22) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_BUS_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 2) | + (0x0 << 3) | + (0x0 << 4) | + (0x10 << 5) | + (0x1 << 10) | + (0x1 << 20) | + (0x1 << 21) | + (0x1 << 22) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_P2P_RX_CLK_REG0_MASK = (0x1 << 0) | (0x1 << 5), + INFRACFG_AO_P2P_RX_CLK_REG0_ON = (0x0 << 0) | (0x1 << 5), + INFRACFG_AO_PERI_BUS_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 10) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21) | + (0x1 << 22) | + (0x1f << 23) | + (0x1 << 31), + INFRACFG_AO_PERI_BUS_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x1f << 5) | + (0x0 << 10) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21) | + (0x1 << 22) | + (0x0 << 23) | + (0x1 << 31), +}; #endif /* SOC_MEDIATEK_MT8186_PLL_H */ diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 7f9d748..7d10e9c 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -436,6 +436,31 @@ write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603); write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603); + /* dcm_infracfg_ao_audio_bus */ + clrsetbits32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_AUDIO_BUS_REG0_MASK, + INFRACFG_AO_AUDIO_BUS_REG0_ON); + + /* dcm_infracfg_ao_icusb_bus */ + clrsetbits32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_ICUSB_BUS_REG0_MASK, + INFRACFG_AO_ICUSB_BUS_REG0_ON); + + /* dcm_infracfg_ao_infra_bus */ + clrsetbits32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_REG0_MASK, + INFRACFG_AO_INFRA_BUS_REG0_ON); + + /* dcm_infracfg_ao_p2p_rx_clk */ + clrsetbits32(&mt8186_infracfg_ao->p2p_rx_clk_on, + INFRACFG_AO_P2P_RX_CLK_REG0_MASK, + INFRACFG_AO_P2P_RX_CLK_REG0_ON); + + /* dcm_infracfg_ao_peri_bus */ + clrsetbits32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_REG0_MASK, + INFRACFG_AO_PERI_BUS_REG0_ON); + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); -- To view, visit https://review.coreboot.org/c/coreboot/+/59338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf Gerrit-Change-Number: 59338 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56322 ) Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 05:45:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
by Karthik Ramasubramanian (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58963 ) Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/58963/comment/093285b2_19bc5d1b PS2, Line 127: preload_microcode Where is it getting called? -- To view, visit https://review.coreboot.org/c/coreboot/+/58963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Gerrit-Change-Number: 58963 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 05:42:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Add helper functions to look up size and type of a file
by Werner Zeh (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jakub Czapiga, Julius Werner. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59312 ) Change subject: cbfs: Add helper functions to look up size and type of a file ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Thank you Julius for this extension! -- To view, visit https://review.coreboot.org/c/coreboot/+/59312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba Gerrit-Change-Number: 59312 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 05:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: RFC: Unify PSP section of cezanne & picasso makefiles
by Martin Roth (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Bao Zheng, Felix Held. Martin Roth has removed Jason Glenesk from this change. ( https://review.coreboot.org/c/coreboot/+/59337 ) Change subject: RFC: Unify PSP section of cezanne & picasso makefiles ...................................................................... Removed reviewer Jason Glenesk. -- To view, visit https://review.coreboot.org/c/coreboot/+/59337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00a8a3d34afeeee08fdcec52c7fa35c885ffc7a6 Gerrit-Change-Number: 59337 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: deleteReviewer

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