coreboot-gerrit November 2021

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Change in coreboot[master]: soc/mediatek/mt8186: add SPM loader
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59341 ) Change subject: soc/mediatek/mt8186: add SPM loader ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 Gerrit-Change-Number: 59341 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 07:33:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Nick Vaccaro, Shon Wang. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59334 to look at the new patch set (#3). Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... mb/google/brya/var/vell: update memory settings BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/Makefile.inc A src/mainboard/google/brya/variants/vell/memory.c 2 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/59334/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 3 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Enable DCM
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59338 ) Change subject: soc/mediatek/mt8186: Enable DCM ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf Gerrit-Change-Number: 59338 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 07:32:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Enable DCM
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59338 ) Change subject: soc/mediatek/mt8186: Enable DCM ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8186/include/soc/pll.h: https://review.coreboot.org/c/coreboot/+/59338/comment/5716f982_8525ea0e PS1, Line 511: enum > Can we write following enum with DEFINE_BITFIELD? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf Gerrit-Change-Number: 59338 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 07:31:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD
by EricR Lai (Code Review) 16 Nov '21

16 Nov '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59348 ) Change subject: mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD ...................................................................... mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD Add MT53E1G32D2NP-046 WT:B SPD. BUG=b:205669003 TEST=Boot up without issues. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: If084a8af941b36a8f3f608271078e32b093d9108 --- M src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc M src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59348/1 diff --git a/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc b/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc index 22436b6..56c4f4f 100644 --- a/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt +# util/spd_tools/src/part_id_gen/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt index abfd12d..927bd60 100644 --- a/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt +# util/spd_tools/src/part_id_gen/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt index 89792ed..7aadba9 100644 --- a/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt @@ -2,3 +2,4 @@ K4UBE3D4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/59348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If084a8af941b36a8f3f608271078e32b093d9108 Gerrit-Change-Number: 59348 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI
by Werner Zeh (Code Review) 16 Nov '21

16 Nov '21

Werner Zeh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59347 ) Change subject: mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI ...................................................................... mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI This board does not have a LPC or eSPI connection to the NC FPGA anymore and therefore IO port 0x80 is not useable for POST codes anymore. Enable the feature of sending the POST codes to the NC FPGA via PCI so that the POST codes are visbile again in coreboot. Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c 3 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/59347/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Gerrit-Change-Number: 59347 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/tests: Add libcbfs/cbfs_core-test test case
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jakub Czapiga, Paul Fagerburg, Julius Werner, Jan Dabros. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58327 ) Change subject: libpayload/tests: Add libcbfs/cbfs_core-test test case ...................................................................... Patch Set 2: (5 comments) File payloads/libpayload/tests/libcbfs/cbfs_core-test.c: https://review.coreboot.org/c/coreboot/+/58327/comment/31b01626_16aa9deb PS2, Line 245: fail() Is fail a function? https://review.coreboot.org/c/coreboot/+/58327/comment/d7822edb_8a23873b PS2, Line 487: test_cbfs_get_handle_file_bigger_than_cbfs Could you explain the purpose of this test? https://review.coreboot.org/c/coreboot/+/58327/comment/a450c6ff_a13279d2 PS2, Line 580: * Space https://review.coreboot.org/c/coreboot/+/58327/comment/5a842337_4a7c723d PS2, Line 672: sizeof(struct cbfs_file) + 16 handle->attribute_offset https://review.coreboot.org/c/coreboot/+/58327/comment/dcbc4840_ca19b9fc PS2, Line 773: assert_null(cbfs_get_contents(handle, &size, 0)); After this call, reset size to 0 for the second call. -- To view, visit https://review.coreboot.org/c/coreboot/+/58327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib246a891242f5a514f2f142699800eeb407de4f9 Gerrit-Change-Number: 58327 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 07:23:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI
by Werner Zeh (Code Review) 16 Nov '21

16 Nov '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59347 ) Change subject: mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI ...................................................................... mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI This board does not have a LPC or eSPI connection to the NC FPGA anymore and therefore IO port 0x80 is not useable for POST codes anymore. Enable the feature of sending the POST codes to the NC FPGA via PCI so that the POST codes are visbile again in coreboot. Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/59347/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig index fbee7b0..0b0ffe5 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig @@ -4,6 +4,7 @@ def_bool y select DRIVER_INTEL_I210 select INTEL_LPSS_UART_FOR_CONSOLE + select NC_FPGA_POST_CODE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" @@ -12,4 +13,19 @@ int default 2 +config EARLY_PCI_BRIDGE_DEVICE + hex + depends on NC_FPGA_POST_CODE + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + depends on NC_FPGA_POST_CODE + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + depends on NC_FPGA_POST_CODE + default 0xfe800000 + endif # BOARD_SIEMENS_MC_EHL1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc index e011999..3036363 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc @@ -4,6 +4,8 @@ romstage-y += memory.c ramstage-y += gpio.c +all-$(CONFIG_NC_FPGA_POST_CODE) += post.c + SPD_SOURCES = mc_ehl1 # 0b000 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \ src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c new file mode 100644 index 0000000..f6029db --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <nc_fpga.h> +#include <types.h> + +void mainboard_post(uint8_t value) +{ + nc_fpga_post(value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Gerrit-Change-Number: 59347 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/siemens/nc_fpga: Add POST code over PCI
by Werner Zeh (Code Review) 16 Nov '21

16 Nov '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59346 ) Change subject: drivers/siemens/nc_fpga: Add POST code over PCI ...................................................................... drivers/siemens/nc_fpga: Add POST code over PCI So far POST codes were mapped on IO port 0x80 inside the NC FPGA which was connected via the LPC bus to the host CPU. On recent x86 generations the LPC bus was replaced with eSPI and not all Siemens boards have the eSPI routed to the NC FPGA. In order to have POST codes visible on those boards the display is accessible via PCI in addition. This patch adds the feature of sending the POST codes to the NC FPGA via a PCI mapped register. Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/siemens/nc_fpga/Kconfig M src/drivers/siemens/nc_fpga/Makefile.inc M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/siemens/nc_fpga/nc_fpga.h A src/drivers/siemens/nc_fpga/nc_fpga_early.c 5 files changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/59346/1 diff --git a/src/drivers/siemens/nc_fpga/Kconfig b/src/drivers/siemens/nc_fpga/Kconfig index 1cd7977..f4f1e97 100644 --- a/src/drivers/siemens/nc_fpga/Kconfig +++ b/src/drivers/siemens/nc_fpga/Kconfig @@ -5,3 +5,8 @@ config NC_FPGA_NOTIFY_CB_READY bool default n + +config NC_FPGA_POST_CODE + bool + default n + select EARLY_PCI_BRIDGE diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc index ac2875f..95ec00a 100644 --- a/src/drivers/siemens/nc_fpga/Makefile.inc +++ b/src/drivers/siemens/nc_fpga/Makefile.inc @@ -1,3 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_SIEMENS_NC_FPGA) += nc_fpga.c + +all-$(CONFIG_NC_FPGA_POST_CODE) += nc_fpga_early.c + +ifeq ($(CONFIG_NC_FPGA_POST_CODE),y) +CPPFLAGS_common += -I$(src)/drivers/siemens/nc_fpga +endif diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 08e8856..0b4c7d4 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -142,9 +142,21 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_fw_done, NULL); #endif +static void nc_fpga_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + + if (CONFIG(NC_FPGA_POST_CODE)) { + /* Re-initialize base address after set_resources for POST display + to work properly.*/ + nc_fpga_remap(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf); + } +} + + static struct device_operations nc_fpga_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = nc_fpga_set_resources, .enable_resources = pci_dev_enable_resources, .init = nc_fpga_init, }; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index 2096de7..39cc04e 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -17,6 +17,7 @@ #define NC_DIAG_FW_DONE 0x10000 #define NC_BL_BRIGHTNESS_OFFSET 0x88 #define NC_BL_PWM_OFFSET 0x8C +#define NC_FPGA_POST_OFFSET 0xE0 #define NC_FANMON_CTRL_OFFSET 0x400 #define MAX_NUM_SENSORS 8 @@ -58,4 +59,7 @@ uint32_t fanmon; } __packed fan_ctrl_t; +void nc_fpga_post(uint8_t value); +void nc_fpga_remap(uint32_t new_mmio); + #endif /* _SIEMENS_NC_FPGA_H_ */ diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c new file mode 100644 index 0000000..6ec0349 --- /dev/null +++ b/src/drivers/siemens/nc_fpga/nc_fpga_early.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmio.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <types.h> + +#include "nc_fpga.h" + +static DEVTREE_CONST uint32_t fpga_bar = CONFIG_EARLY_PCI_MMIO_BASE; +static bool nc_fpga_present = false; + +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0); + uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID); + + if (id != (0x4091 << 16 | PCI_VENDOR_ID_SIEMENS)) + return -1; + + /* Setup base address for BAR0. */ + pci_s_write_config32(pci_dev, PCI_BASE_ADDRESS_0, mmio_base); + /* Enable memory access for pci_dev. */ + u16 reg16 = pci_s_read_config16(pci_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_s_write_config16(pci_dev, PCI_COMMAND, reg16); + nc_fpga_present = true; + + return 0; +} + +void nc_fpga_remap(uint32_t new_mmio) +{ +#if ENV_RAMSTAGE + fpga_bar = new_mmio; +#endif +} + +void nc_fpga_post(uint8_t value) +{ + /* The function pci_earyl_device_probe is called in bootblock and romstage. Make sure + that in these stages the initialization code was successful before the POST code + value is written to the register. */ + if ((ENV_BOOTBLOCK || ENV_ROMSTAGE) && nc_fpga_present == false) + return; + write32((void *)(fpga_bar + NC_FPGA_POST_OFFSET), value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0 Gerrit-Change-Number: 59346 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method
by Ravi kumar (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56093 to look at the new patch set (#38). Change subject: mb/google/herobrine: Initialize USB by calling SOC method ...................................................................... mb/google/herobrine: Initialize USB by calling SOC method Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 --- M src/mainboard/google/herobrine/mainboard.c M src/mainboard/google/herobrine/romstage.c 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56093/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/56093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Gerrit-Change-Number: 56093 Gerrit-PatchSet: 38 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021