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Change subject: soc/qualcomm/common/usb: Add support for common USB driver
......................................................................
soc/qualcomm/common/usb: Add support for common USB driver
Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
---
M src/mainboard/google/trogdor/mainboard.c
M src/mainboard/google/trogdor/romstage.c
A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h
A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h
A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h
A src/soc/qualcomm/common/include/soc/usb/usb_common.h
R src/soc/qualcomm/common/usb/qmpv3_usb_phy.c
A src/soc/qualcomm/common/usb/qmpv4_usb_phy.c
A src/soc/qualcomm/common/usb/qusb_phy.c
A src/soc/qualcomm/common/usb/snps_usb_phy.c
A src/soc/qualcomm/common/usb/usb.c
M src/soc/qualcomm/sc7180/Makefile.inc
D src/soc/qualcomm/sc7180/include/soc/usb.h
13 files changed, 1,027 insertions(+), 416 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/38
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Hello Shelley Chen, build bot (Jenkins), Taniya Das, mturney mturney, Julius Werner,
I'd like you to reexamine a change. Please visit
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Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme
......................................................................
qualcomm/sc7280: gpio: Support eGPIO scheme
eGPIO is a scheme which allows special power island domain IOs to be
reused as regular chip GPIOs by muxing regular TLMM functions with
Island Domain functions. Allow the eGPIO to be configured via
gpio_configure API to be used as a TLMM gpio.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9
---
M src/soc/qualcomm/common/gpio.c
M src/soc/qualcomm/common/include/soc/gpio_common.h
2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58580/7
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
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Change subject: soc/mediatek/mt8186: Enable DCM
......................................................................
soc/mediatek/mt8186: Enable DCM
DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.
TEST=build pass and check register ok
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang(a)mediatek.corp-partner.google.com>
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
---
M src/soc/mediatek/mt8186/include/soc/pll.h
M src/soc/mediatek/mt8186/pll.c
2 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59338/2
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Change subject: soc/intel/alderlake: Add _DSM method for CNVi WiFi
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/acpi/cnvi_wifi.asl:
PS7:
> This should be generated at runtime using the acpigen library; therefore this should go in `drivers/ […]
okay let me check.
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Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58132 )
Change subject: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration
......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/58132/comment/c2ef6b7d_7d79130f
PS6, Line 532: /* CNVi DDR RFIM Enable/Disable
: * Default 0. Setting this to 1 disables CNVi DDR RFIM.
: */
: bool CnviDdrRfimDisable;
> I think we should invert the polarity of this, and have it be an `Enable` option
Right now it is by default enable from FSP. that's why i gave option to disable from devicetree if needed.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/58132/comment/d23482b0_734a15cf
PS6, Line 211: (config->CnviDdrRfimDisable)
> nit: parentheses not required
Ack
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Hello build bot (Jenkins), Henry Sun, Wisley Chen,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera
......................................................................
mb/google/dedede/var/drawcia: Add fw_config probe for MIPI camera
Add fw_config probe for MIPI camera
BUG=b:205920110
TEST=FW_NAME=drawcia emerge-dedede coreboot
Change-Id: I89d84b6eb77c18b36b1ff946cec057889013c58f
Signed-off-by: RobertChen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
1 file changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/59333/5
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 )
Change subject: ec/starlabs: Add standardised ITE EC support
......................................................................
Patch Set 41:
(2 comments)
File src/ec/starlabs/merlin/Kconfig:
https://review.coreboot.org/c/coreboot/+/58343/comment/37cc2461_b4438346
PS37, Line 29: bool "Fan device"
> Same as above.
Done
File src/ec/starlabs/merlin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58343/comment/6e123ffe_bcb8ee25
PS37, Line 9: $(VARIANT_DIR)
> Like so?
Done
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