coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: soc/mediatek/mt8186: add SPM loader
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59341 ) Change subject: soc/mediatek/mt8186: add SPM loader ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: > @yu-ping, […] Sure, I thought I did. -- To view, visit https://review.coreboot.org/c/coreboot/+/59341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 Gerrit-Change-Number: 59341 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:22:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/redrix: Correct WWAN power sequence
by Chen Wisley (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Chen Wisley. Hello build bot (Jenkins), Tim Wawrzynczak, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59267 to look at the new patch set (#4). Change subject: mb/google/brya/var/redrix: Correct WWAN power sequence ...................................................................... mb/google/brya/var/redrix: Correct WWAN power sequence Correct the WWAN power sequence to meet spec BUG=b:206079177 TEST=build Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/redrix/Makefile.inc M src/mainboard/google/brya/variants/redrix/gpio.c M src/mainboard/google/brya/variants/redrix/include/variant/gpio.h 4 files changed, 34 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/59267/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150 Gerrit-Change-Number: 59267 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: libpayload/tests: Add libcbfs/cbfs_core-test test case
by Jakub Czapiga (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Yu-Ping Wu. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58327 ) Change subject: libpayload/tests: Add libcbfs/cbfs_core-test test case ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Yu-Ping, Thanks for review, but this test probably will not land in it's current form. We want to remove cbfs_media, which is a base for the old CBFS API, which also will be removed in the near future. -- To view, visit https://review.coreboot.org/c/coreboot/+/58327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib246a891242f5a514f2f142699800eeb407de4f9 Gerrit-Change-Number: 58327 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by build bot (Jenkins) (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... Patch Set 8: (1 comment) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133414): https://review.coreboot.org/c/coreboot/+/58545/comment/b822a900_94a44d41 PS8, Line 27: if (soc_modem_carve_out(&start, &end)) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:12:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Makefile.inc: Split of image generation in multiple targets
by Arthur Heymans (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Arthur Heymans, Martin Roth, Yu-Ping Wu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56114 ) Change subject: Makefile.inc: Split of image generation in multiple targets ...................................................................... Patch Set 4: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/56114/comment/9aaaf6d9_d7e331f6 PS4, Line 1129: mv $@.tmp $@ > I think the point of this is to prevent corrupt or incomplete data written to $@, but you're changing that in this patch. I'm not sure what's the right way to fix it though. Why would corrupt or incomplete data be written to $(obj)/coreboot.pre? I suspect it's there to be able to analyze the .tmp file as an intermediate file if things fail when adding files to cbfs. -- To view, visit https://review.coreboot.org/c/coreboot/+/56114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If36aee0bd2f75f3941b3bc424a7ec6c775eb1353 Gerrit-Change-Number: 56114 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/00fe669b_2d11d850 PS8, Line 112: struct pmc_thermal_config { : void (*func)(uintptr_t addr, uint32_t data); : uint16_t offset; : uint32_t value; : } config[] = { : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_CTEN, : .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_ECRPTEN, : .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT : | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK, : }, : { : .func = write32p, : .offset = PMC_PWRM_THERMAL_TL, : .value = pch_get_ltt_value(dev) | PMC_PWRM_THERMAL_TL_TTEN : | PMC_PWRM_THERMAL_TL_TLLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_PHLC, : .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_TLEN, : .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK, : }, : }; > Is this really necessary for ~10 10 lines of code ? > > ``` > setbits32(pmc_bar + PMC_PWRM_THERMAL_CTEN, PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK); > setbits32(pmc_bar + PMC_PWRM_THERMAL_ECRPTEN, PMC_PWRM_THERMAL_ECRPTEN_EN_RPT > | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK); > ``` > etc. ?\ This can be done for sure, even at first patch set I have done the same but for few reason, I have prefer to create a structure as below: 1. More than one bit fields are getting set and with such bigger macro names, its difficult to follow what all bits we are programming into which register? 2. Making register offset clearly visible to know which offset we are programming. 3. Although there are majority of programing to set/reset certain bits but we might need to perform thermal threshold level write into the register hence wish to make it clear the underlying operations. TL.T2L[28:20]: Program to the Throttle 2 temperature threshold level. TL.T1L[18:10]: Program to the Throttle 1 temperature threshold level. TL.T0L[8:0]: Program to the Throttle 0 temperature threshold level. looks like we don't need helper function thermal_rmw32/thermal_or32 as we could do the same using clrsetbits32 and setbits32. Please let me know if you still prefers to program as suggested by you. I don't mind to change the way its being done, as all does the same register programing with even or little improvement of code readability 😊 > > Also should any others of these settings be configurable, e.g. EC thermal reporting? Please take a look into https://review.coreboot.org/c/coreboot/+/59209/8/src/soc/intel/common/block… // Enable thermal reporting to an EC over SMBus or eSPI and PMC. // Set bit[0] of ECRPTEN register to 1. https://review.coreboot.org/c/coreboot/+/59209/comment/0ce69d68_1a63a7be PS8, Line 106: /* Enable thermal sensor power management using PMC PCH device */ : static void pch_pmc_thermal_configuration(void) : { : struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); : uintptr_t pmc_bar = soc_read_pmc_base(); : : struct pmc_thermal_config { : void (*func)(uintptr_t addr, uint32_t data); : uint16_t offset; : uint32_t value; : } config[] = { : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_CTEN, : .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_ECRPTEN, : .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT : | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK, : }, : { : .func = write32p, : .offset = PMC_PWRM_THERMAL_TL, : .value = pch_get_ltt_value(dev) | PMC_PWRM_THERMAL_TL_TTEN : | PMC_PWRM_THERMAL_TL_TLLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_PHLC, : .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_TLEN, : .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK, : }, : }; : : for (int i = 0; i < ARRAY_SIZE(config); i++) : config[i].func(pmc_bar + config[i].offset, config[i].value); : } : > That could work, if this will be part of PMC in the future. […] I kind of agree with both of you. @Tim, you are right that there is no dedicated thermal device from TGL so maybe move this code into PMC and call it separately. @Eric, for now what visibility I have in the codebase, looks like thermal configuration going to stay behind PMC for longer 😊 The only reason, I have thought prior to moving the thermal configuration for latest SOC even there is no thermal device are: 1. Maintain a programming parity with its purpose rather than the actual device. While debugging if we are seeing any thermal related issue, it would be easy to just grep "*thermal*.c" rather pmc.c 😊 2. Also, you can understand the amount of code reusability we could achieve irrespective of whether we have a dedicated thermal device or device register behind PMC. The underlying thermal threshold logic or getting the thermal configuration value from different mb code, we could easily reuse from here example: get_thermal_trip_temp() and pch_get_ltt_value() etc. 3. Making a unified call irrespective of different SoC can land into pch_thermal_configuration() would help to make us understand the change in thermal configuration from SOC side over generation and we could share the feedback to the SoC team about good or bad in this change. The only downside is the W/A that we have here: https://review.coreboot.org/c/coreboot/+/59209/8/src/soc/intel/common/block… I believe for the benefit of making things common (meaningfully) we can pay that much. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:07:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8186: add SPM loader
by Rex-BC Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59341 ) Change subject: soc/mediatek/mt8186: add SPM loader ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @yu-ping, is this patch ok to +2? -- To view, visit https://review.coreboot.org/c/coreboot/+/59341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 Gerrit-Change-Number: 59341 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ChromeOS: Add DECLARE_x_CROS_GPIOS()
by Kyösti Mälkki (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58899 to look at the new patch set (#8). Change subject: ChromeOS: Add DECLARE_x_CROS_GPIOS() ...................................................................... ChromeOS: Add DECLARE_x_CROS_GPIOS() Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/variants/baseboard/brask/gpio.c M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/deltaur/variants/baseboard/gpio.c M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/gpio.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h 51 files changed, 72 insertions(+), 258 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/58899/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/58899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Gerrit-Change-Number: 58899 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ChromeOS: Promote variant_cros_gpio()
by Kyösti Mälkki (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nick Vaccaro, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58897 to look at the new patch set (#9). Change subject: ChromeOS: Promote variant_cros_gpio() ...................................................................... ChromeOS: Promote variant_cros_gpio() The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/majolica/chromeos.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/glados/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/chromeos.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/adlrvp/gpio_m.c M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 67 files changed, 88 insertions(+), 313 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/58897/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/58897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Gerrit-Change-Number: 58897 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by Kyösti Mälkki (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58896 to look at the new patch set (#7). Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... ChromeOS: Add legacy mainboard_ec_running_ro() TBD: S3 resume path case Motivation is to have mainboard_chromeos_acpi_generate() do nothing else than fill ACPI \OIPG package. Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/bootmode.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 7 files changed, 34 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/58896/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021