coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Makefile.inc: Split of image generation in multiple targets
by Yu-Ping Wu (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Arthur Heymans, Martin Roth. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56114 ) Change subject: Makefile.inc: Split of image generation in multiple targets ...................................................................... Patch Set 4: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/56114/comment/0b5913f7_9a597234 PS4, Line 1129: mv $@.tmp $@ > Why would corrupt or incomplete data be written to $(obj)/coreboot.pre? I mean, when 'make' is unexpectedly terminated, or a recipe command fails, there's no guarantee on the content. In that case, 'make' might consider the corrupted target file as up-to-date. -- To view, visit https://review.coreboot.org/c/coreboot/+/56114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If36aee0bd2f75f3941b3bc424a7ec6c775eb1353 Gerrit-Change-Number: 56114 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:37:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Initialize SPM
by Hung-Te Lin (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59342 ) Change subject: mb/google/corsola: Initialize SPM ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59342/comment/8093ce81_7cd1d5ba PS2, Line 9: This patch adds support for SPM. This adds 55ms to the boot time. Initialize SPM (XXX XXX XXX) in RAM stage. This adds 55ms to the boot time. -- To view, visit https://review.coreboot.org/c/coreboot/+/59342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I822417f7a679107760b202dd43fb79d1934940bd Gerrit-Change-Number: 59342 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:35:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: initialize sspm
by Hung-Te Lin (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59340 ) Change subject: soc/mediatek/mt8186: initialize sspm ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59340/comment/4c7a6469_e9e81849 PS2, Line 7: sspm SSPM https://review.coreboot.org/c/coreboot/+/59340/comment/a5ebf23b_cbf5d6cc PS2, Line 9: Add drivers of loading sspm.bin. Please also explain what is SSPM, also explain that it needs a specific firmware that we have to load and initialize in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/59340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391 Gerrit-Change-Number: 59340 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:32:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Split of image generation in multiple targets
by Arthur Heymans (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Martin Roth, Arthur Heymans, Yu-Ping Wu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56114 ) Change subject: Makefile.inc: Split of image generation in multiple targets ...................................................................... Patch Set 4: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/56114/comment/19deeec7_d4411d2d PS4, Line 1129: mv $@.tmp $@ > It works around race conditions: when building in parallel, some gnu make versions look for a file's existence to determine that steps waiting on that file are good to go. > > Poses to be a problem if these files aren't complete yet (but the process writing them takes a while). The diversion via .tmp has nothing to do with debuggability. Ah I think I understand. Thanks for explaining. -- To view, visit https://review.coreboot.org/c/coreboot/+/56114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If36aee0bd2f75f3941b3bc424a7ec6c775eb1353 Gerrit-Change-Number: 56114 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:32:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by EricR Lai (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/e13fe30a_23e2a06f PS8, Line 112: struct pmc_thermal_config { : void (*func)(uintptr_t addr, uint32_t data); : uint16_t offset; : uint32_t value; : } config[] = { : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_CTEN, : .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_ECRPTEN, : .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT : | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK, : }, : { : .func = write32p, : .offset = PMC_PWRM_THERMAL_TL, : .value = pch_get_ltt_value(dev) | PMC_PWRM_THERMAL_TL_TTEN : | PMC_PWRM_THERMAL_TL_TLLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_PHLC, : .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_TLEN, : .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK, : }, : }; > > Is this really necessary for ~10 10 lines of code ? […] I kind like this structure, like we do the thermal config. You can just maintain the array to add more setting if needed rather than add in the end of sector. Very clear to me (stupid guys). I really don't like to read long long parameters setbits32(pmc_bar + PMC_PWRM_THERMAL_ECRPTEN, PMC_PWRM_THERMAL_ECRPTEN_EN_RPT | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK); balbal... -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:31:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST] mb/google/brya/var/redrix: exchange i2c port for touchscreen/cr50
by Chen Wisley (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59349 to look at the new patch set (#2). Change subject: [TEST] mb/google/brya/var/redrix: exchange i2c port for touchscreen/cr50 ...................................................................... [TEST] mb/google/brya/var/redrix: exchange i2c port for touchscreen/cr50 Exchange i2c port for touchscreen and cr50. BUG=none TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I8f3a1a20d98cd4cbfa6fc7cc31cb688761f9f763 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59349/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f3a1a20d98cd4cbfa6fc7cc31cb688761f9f763 Gerrit-Change-Number: 59349 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [TEST] mb/google/brya/var/redrix: exchange i2c port for touchscreen/cr50
by Chen Wisley (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59349 to review the following change. Change subject: [TEST] mb/google/brya/var/redrix: exchange i2c port for touchscreen/cr50 ...................................................................... [TEST] mb/google/brya/var/redrix: exchange i2c port for touchscreen/cr50 Exchange i2c port for touchscreen and cr50. BUG=none TEST=build Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I8f3a1a20d98cd4cbfa6fc7cc31cb688761f9f763 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/59349/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 77e44e3..33c6695 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -255,8 +255,17 @@ register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 0x15 on end + device i2c 0x15 on + probe HW_PHASE HW_PRE_DVT + end end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on + probe HW_PHASE HW_AFTER_DVT + end + end end device ref i2c2 on chip drivers/intel/mipi_camera @@ -358,6 +367,36 @@ end end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on + probe HW_PHASE HW_PRE_DVT + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x15 on + probe HW_PHASE HW_AFTER_DVT + end + end + end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/59349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f3a1a20d98cd4cbfa6fc7cc31cb688761f9f763 Gerrit-Change-Number: 59349 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile.inc: Split of image generation in multiple targets
by Patrick Georgi (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Arthur Heymans, Martin Roth, Yu-Ping Wu. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56114 ) Change subject: Makefile.inc: Split of image generation in multiple targets ...................................................................... Patch Set 4: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/56114/comment/b8ebf393_90ff47ec PS4, Line 1129: mv $@.tmp $@ > > I think the point of this is to prevent corrupt or incomplete data written to $@, but you're chang […] It works around race conditions: when building in parallel, some gnu make versions look for a file's existence to determine that steps waiting on that file are good to go. Poses to be a problem if these files aren't complete yet (but the process writing them takes a while). The diversion via .tmp has nothing to do with debuggability. -- To view, visit https://review.coreboot.org/c/coreboot/+/56114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If36aee0bd2f75f3941b3bc424a7ec6c775eb1353 Gerrit-Change-Number: 56114 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:26:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: WIP soc: Added dram information to cbmem WIP
by build bot (Jenkins) (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: WIP soc: Added dram information to cbmem WIP ...................................................................... Patch Set 3: (80 comments) File src/soc/qualcomm/common/qclib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/2a3cab91_0e92188a PS3, Line 27: #if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/1b9f9485_bb3b4cd2 PS3, Line 30: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/3057ac40_71ea59af PS3, Line 31: uint64_t type; // enum that differentiates DDR3, LPDDR3, LPDDR4, etc. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/18af3e6a_2363aeb4 PS3, Line 32: uint64_t num_channels; // To know how may channels are available. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/282bd7de_454fd97a PS3, Line 33: uint64_t reserved[6]; // Reserved [6] please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/b217870f_cd847da2 PS3, Line 34: struct please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/481a5992_b3737594 PS3, Line 35: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/aabacd0b_e3aa362d PS3, Line 35: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/37db3e7d_32d99f77 PS3, Line 36: uint64_t density; // Total density Seen on channel code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/3b196c72_74bd3a60 PS3, Line 36: uint64_t density; // Total density Seen on channel please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/1af82e1a_1688533d PS3, Line 37: uint64_t io_width; // JEDEC MR8 - io width code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/97e8146c_c5f72c46 PS3, Line 37: uint64_t io_width; // JEDEC MR8 - io width please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/f204a8bb_466ef8f6 PS3, Line 38: uint64_t manufacturer_id; // JEDEC MR5 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/0451a206_d50f26f7 PS3, Line 38: uint64_t manufacturer_id; // JEDEC MR5 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/f0609460_f2c7b196 PS3, Line 39: uint64_t revision_id[2]; // JEDEC MR6, MR7 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/70002217_0380a861 PS3, Line 39: uint64_t revision_id[2]; // JEDEC MR6, MR7 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/52d9c20d_99ad6eb7 PS3, Line 40: uint64_t reserved[4]; // Reserved code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/c035b0b9_e5f44dc4 PS3, Line 40: uint64_t reserved[4]; // Reserved please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/4f8e483e_56c22f73 PS3, Line 41: uint64_t serial_id[8]; // for potential future LPDDR5 expansion code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ce565650_1702aa65 PS3, Line 41: uint64_t serial_id[8]; // for potential future LPDDR5 expansion please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/2d3fc400_214a2504 PS3, Line 42: } channels[DDR_MAX_NUM_CH_TEST]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/cd1f9a21_9b784134 PS3, Line 43: }dram_info; space required after that close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/68fbd94f_d30bba96 PS3, Line 48: /* Save MEM CHIP info in SRAM region to share with ramstage */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/33b5842f_01b959ec PS3, Line 49: mem_chip_offset = (void *)te->blob_address; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/c15b3a92_504e2a46 PS3, Line 49: mem_chip_offset = (void *)te->blob_address; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/3f4db4df_16826fb6 PS3, Line 50: mem_chip_size = te->size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/f82de36e_e2917b02 PS3, Line 50: mem_chip_size = te->size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/096507df_95b24e9e PS3, Line 55: printk(BIOS_INFO, "%s:%s: Test Code to print memchip information before adding cbmem_add\n", __FILE__, __func__); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/33057bfb_31f7976a PS3, Line 56: memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/2196965f_9f2f94e5 PS3, Line 56: memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/f9a5523e_b84ef4b4 PS3, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/6ede1534_98c8b18b PS3, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/593f03da_662954ec PS3, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/2d6454c8_a26cc63a PS3, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/511cd475_6ae9d532 PS3, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/49c7b481_339cd17e PS3, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/66ce93f2_c47c77b6 PS3, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ed91b202_2050998e PS3, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/5eeeb501_efc4827f PS3, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ec52a828_7fae0a96 PS3, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/7696a1fd_3e358ab3 PS3, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/b281386c_3c01109b PS3, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ab41e4b6_47d0385e PS3, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/323d0fd1_ac9ea436 PS3, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/c13052d4_d3bc8322 PS3, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ae9bba23_d1751201 PS3, Line 66: void *mem_region_base; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ae7265d1_cc803d3e PS3, Line 66: void *mem_region_base; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ba6c75a7_baaccaeb PS3, Line 69: mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/60c16dc3_ffbf61fe PS3, Line 69: mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/70f072c0_9c963bbf PS3, Line 70: ASSERT(mem_region_base != NULL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/454f4f49_a520a6ce PS3, Line 70: ASSERT(mem_region_base != NULL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/b8b061f0_8242a6fe PS3, Line 72: /* Migrate the data into CBMEM */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/88319aa1_85ad6c8e PS3, Line 73: memcpy(mem_region_base, mem_chip_offset, mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/8d65e273_ad44624d PS3, Line 73: memcpy(mem_region_base, mem_chip_offset, mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/41f43376_44943f4f PS3, Line 77: /* Test Code to print memchip information after adding cbmem_addd */ 'addd' may be misspelled - perhaps 'add'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/6ea9e172_4b34eb91 PS3, Line 78: printk(BIOS_INFO, "%s:%s: Test Code to print memchip information after adding cbmem_add\n", __FILE__, __func__); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/2284e691_88d78a44 PS3, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/5d40337f_de083776 PS3, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/37787f7d_86cbe631 PS3, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/3a97333f_c247fe80 PS3, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); space prohibited before that ',' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/6e600160_182700ee PS3, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/eee52ddd_fe6cbcd9 PS3, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/7a63d90f_9247f9e3 PS3, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/ebb00ab7_68637ede PS3, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/7a5dae3b_4660a167 PS3, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/0dcf095e_a9bbd760 PS3, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/a1b49e09_3ae5554c PS3, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/95254064_fedf94d9 PS3, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/f60eef39_8a5bca4b PS3, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/f14eb484_6e6c8b69 PS3, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/687cfd24_9f652d52 PS3, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/bf959b74_9724a1d0 PS3, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/41102c88_649d515b PS3, Line 157: sizeof(te->name))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/52aa6be7_dbc36faf PS3, Line 157: sizeof(te->name))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/d3e92b00_eb59f32a PS3, Line 158: write_mem_chip_information(te); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/9519b3c5_ee7a06bb PS3, Line 158: write_mem_chip_information(te); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/a8803352_51847e95 PS3, Line 213: qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/8deecfb9_cc5db60c PS3, Line 213: qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/166ee144_f6254676 PS3, Line 214: _mem_chip_info, REGION_SIZE(mem_chip_info), 0); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133419): https://review.coreboot.org/c/coreboot/+/59195/comment/870c24d6_34fd8b27 PS3, Line 214: _mem_chip_info, REGION_SIZE(mem_chip_info), 0); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 08:25:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP libpayload: Parse DDR Information through coreboot tables WIP
by build bot (Jenkins) (Code Review) 16 Nov '21

16 Nov '21

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coreboot-gerrit November 2021