coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/alderlake: enable gpio locking
by Nick Vaccaro (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58352 to look at the new patch set (#13). Change subject: soc/intel/alderlake: enable gpio locking ...................................................................... soc/intel/alderlake: enable gpio locking This change supplies a list of ADL gpios that are connected to non-host (x86) controllers and should be locked after initial configuration. Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking. BUG=b:210430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that brya0 boots successfully to kernel. Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/gpio.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/58352/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/58352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee Gerrit-Change-Number: 58352 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/model_1067x: Use apic exposed in static.c directly
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59317 to review the following change. Change subject: cpu/intel/model_1067x: Use apic exposed in static.c directly ...................................................................... cpu/intel/model_1067x: Use apic exposed in static.c directly This allows for buildtime checking of the presence of the chip_config. Change-Id: Ifa83ccf6033cbb135c7ec2e9593596dba4c6e3b5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/model_1067x_init.c 1 file changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/59317/1 diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 3e4de1f..9736692 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -30,10 +30,8 @@ { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - const struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; + /* pointer to CPU configuration. */ + const struct cpu_intel_model_1067x_config *const conf = config_of(__apic_acac_0); /* Is C5 requested and supported? */ const int c5 = conf && conf->c5 && @@ -88,10 +86,8 @@ { msr_t msr; - /* Find pointer to CPU configuration. */ - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - struct cpu_intel_model_1067x_config *const conf = - (lapic && lapic->chip_info) ? lapic->chip_info : NULL; + /* pointer to CPU configuration. */ + const struct cpu_intel_model_1067x_config *const conf = config_of(__apic_acac_0); msr = rdmsr(MSR_EXTENDED_CONFIG); /* Super LFM supported? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa83ccf6033cbb135c7ec2e9593596dba4c6e3b5 Gerrit-Change-Number: 59317 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/vell: Generate LP5 RAM ID
by Tim Wawrzynczak (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Kevin Chiu, Nick Vaccaro, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59288 ) Change subject: mb/google/brya/var/vell: Generate LP5 RAM ID ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49745948ebdb25fd98e285defd75714f80271968 Gerrit-Change-Number: 59288 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 19:21:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpu.c: Remove unused variables
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Patrick Rudolph, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58602 ) Change subject: soc/intel/xeon_sp/cpu.c: Remove unused variables ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/58602/comment/6e327a4b_eee551c3 PS1, Line 204: intel_update_microcode_from_cbfs > This has an extra spinlock, does it matter? right, that's a functional difference indeed... Anyway all microcode is already updated by this point anyway... -- To view, visit https://review.coreboot.org/c/coreboot/+/58602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id809cd78fb9da98b9514fcf8d8057dccf2987d23 Gerrit-Change-Number: 58602 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 19:16:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/haswell: Remove the fake lapic
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58604 ) Change subject: cpu/intel/haswell: Remove the fake lapic ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/haswell/acpi.c: https://review.coreboot.org/c/coreboot/+/58604/comment/699ef39d_639da74e PS1, Line 175: s0ix_enable > +1 I think that would be a great addition and help clean up some of the confusion. Done: CB:59313 -- To view, visit https://review.coreboot.org/c/coreboot/+/58604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69f9c1fe71a773e1fba0942d8a785b6ad26dd9a0 Gerrit-Change-Number: 58604 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 19:13:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/model_206ax: Use static.c exposed lapic 0
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59316 to review the following change. Change subject: cpu/intel/model_206ax: Use static.c exposed lapic 0 ...................................................................... cpu/intel/model_206ax: Use static.c exposed lapic 0 Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c 3 files changed, 2 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59316/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f1d03c8..2281229 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -97,16 +97,7 @@ static void generate_C_state_entries(void) { - struct device *lapic; - struct cpu_intel_model_206ax_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; + struct cpu_intel_model_206ax_config *conf = config_of(config_of_lapic()); const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 4fff04a..1120823 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - struct cpu_intel_model_206ax_config { int acpi_c1; /* ACPI C1 */ int acpi_c2; /* ACPI C2 */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38..9602980 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -216,16 +216,9 @@ static void configure_thermal_target(void) { - struct cpu_intel_model_206ax_config *conf; - struct device *lapic; + struct cpu_intel_model_206ax_config *conf = config_of(config_of_lapic()); msr_t msr; - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Gerrit-Change-Number: 59316 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_2065x: Use static.c exposed lapic 0
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59315 to review the following change. Change subject: cpu/intel/model_2065x: Use static.c exposed lapic 0 ...................................................................... cpu/intel/model_2065x: Use static.c exposed lapic 0 Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/chip.h M src/cpu/intel/model_2065x/model_2065x_init.c 2 files changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59315/1 diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index 4ee91f6..9e89793 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - struct cpu_intel_model_2065x_config { int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e77f9aa..9488b86 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -23,16 +23,9 @@ static void configure_thermal_target(void) { - struct cpu_intel_model_2065x_config *conf; - struct device *lapic; + const struct cpu_intel_model_2065x_config *conf = config_of(config_of_lapic()); msr_t msr; - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Gerrit-Change-Number: 59315 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/haswell/acpi.c: Use static.c exposed lapic 0
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59314 to review the following change. Change subject: cpu/haswell/acpi.c: Use static.c exposed lapic 0 ...................................................................... cpu/haswell/acpi.c: Use static.c exposed lapic 0 Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 3 files changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59314/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index f20d446..711f372 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -168,12 +168,7 @@ if (!haswell_is_ult()) return false; - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - - if (!lapic || !lapic->chip_info) - return false; - - const struct cpu_intel_haswell_config *conf = lapic->chip_info; + const struct cpu_intel_haswell_config *conf = config_of(config_of_lapic()); return conf->s0ix_enable; } diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 776e239..5f2324c 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - #include <stdbool.h> #include <stdint.h> diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index d4f3587..872c728 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -179,13 +179,8 @@ struct cpu_vr_config vr_config = { 0 }; msr_t msr; - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - - if (lapic && lapic->chip_info) { - const struct cpu_intel_haswell_config *conf = lapic->chip_info; - - vr_config = conf->vr_config; - } + const struct cpu_intel_haswell_config *conf = config_of(config_of_lapic()); + vr_config = conf->vr_config; printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -452,16 +447,9 @@ static void configure_thermal_target(void) { - struct cpu_intel_haswell_config *conf; - struct device *lapic; + const struct cpu_intel_haswell_config *conf = config_of(config_of_lapic()); msr_t msr; - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/sconfig: Expose apic devices
by Arthur Heymans (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59313 to review the following change. Change subject: util/sconfig: Expose apic devices ...................................................................... util/sconfig: Expose apic devices Expose apic devices in static.c such that fake 0xACAC lapics are not needed in most cases. Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/device/device.h M util/sconfig/main.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/59313/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 237d836..d582ed0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -391,6 +391,7 @@ * Returns pointer to config structure of root device (B:D:F = 0:00:0) defined by * sconfig in static.{h/c}. */ +#define config_of_lapic() __apic_0000_0 #define config_of_soc() __pci_0_00_0_config void enable_static_device(struct device *dev); diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 1de98d4..94292b8 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1361,6 +1361,13 @@ ptr->path_a, ptr->path_b, ptr->name); } + if (ptr->bustype == APIC) { + fprintf(head, "extern DEVTREE_CONST struct device *const __apic_%04x_%d;\n", + ptr->path_a, ptr->path_b); + fprintf(fil, "DEVTREE_CONST struct device *const __apic_%04x_%d = &%s;\n", + ptr->path_a, ptr->path_b, ptr->name); + } + if (ptr->alias) { fprintf(head, "extern DEVTREE_CONST struct device *const %s_ptr;\n", ptr->name); fprintf(fil, "DEVTREE_CONST struct device *const %s_ptr = &%s;\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
by Karthik Ramasubramanian (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59053 ) Change subject: mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252 Gerrit-Change-Number: 59053 Gerrit-PatchSet: 4 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 19:10:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021