coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by EricR Lai (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 16:26:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/include/intelblocks/thermal.h: https://review.coreboot.org/c/coreboot/+/59209/comment/8002ad08_0e47ce31 PS6, Line 6: #define PMC_PWRM_THERMAL_CTEN 0x150c /* Catastrophic Trip Point Enable */ > nits: can we align the comment :p should be easier to read. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 16:23:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Use address mode
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59308 ) Change subject: amdfwtool: Use address mode ...................................................................... Patch Set 1: (5 comments) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133307): https://review.coreboot.org/c/coreboot/+/59308/comment/73e14183_f20bb2f1 PS1, Line 355: ((mode) == 2 ? (offset) - ctx.current_table : (offset)) )) space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133307): https://review.coreboot.org/c/coreboot/+/59308/comment/4c9c32bf_a3bbfc57 PS1, Line 689: pspdir->entries[count].address_mode = pspdir->header.additional_info_fields.address_mode; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133307): https://review.coreboot.org/c/coreboot/+/59308/comment/2b878418_326f99de PS1, Line 741: pspdir->entries[count].address_mode = pspdir->header.additional_info_fields.address_mode; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133307): https://review.coreboot.org/c/coreboot/+/59308/comment/343e5d3c_6d4d395b PS1, Line 947: biosdir->entries[count].address_mode = biosdir->header.additional_info_fields.address_mode; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133307): https://review.coreboot.org/c/coreboot/+/59308/comment/227c58ae_b194a271 PS1, Line 1004: biosdir->entries[count].address_mode = biosdir->header.additional_info_fields.address_mode; line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Gerrit-Change-Number: 59308 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Mon, 15 Nov 2021 16:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT ...................................................................... soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT This patch creates a helper function `thermal_rmw32` to set thermal device Low Temp Threshold (LTT) value. Also, modified `pch_get_ltt_value()` return type from uint16_t to uint32_t. TEST=Able to build and boot hatch and adlrvp with this change. Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/59310/1 diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 6211f35..df01811 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -23,7 +23,7 @@ } /* PCH Low Temp Threshold (LTT) */ -static uint16_t pch_get_ltt_value(struct device *dev) +static uint32_t pch_get_ltt_value(struct device *dev) { uint8_t thermal_config; @@ -37,10 +37,19 @@ return GET_LTT_VALUE(thermal_config); } +static void thermal_rmw32(uintptr_t addr, uint32_t anddata, uint32_t ordata) +{ + uint32_t data32; + + data32 = read32p(addr); + data32 &= anddata; + data32 |= ordata; + write32p(addr, data32); +} + /* Enable thermal sensor power management */ void pch_thermal_configuration(void) { - uint16_t reg16; uintptr_t thermalbar; uintptr_t thermalbar_pm; struct device *dev; @@ -65,9 +74,5 @@ thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - reg16 = read16((uint16_t *)thermalbar_pm); - reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; - /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(dev); - write16((uint16_t *)thermalbar_pm, reg16); + thermal_rmw32(thermalbar_pm, ~CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value(dev)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/../thermal: Drop `ltt_value` local variable
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59309 ) Change subject: soc/intel/../thermal: Drop `ltt_value` local variable ...................................................................... soc/intel/../thermal: Drop `ltt_value` local variable Using the `GET_LTT_VALUE` macro directly instead of 'ltt_value' local variable. Change-Id: I791766bf2a78fa30dbba8cf4ad8a50e44f0e73ed Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59309/1 diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index f886995..6211f35 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -11,6 +11,7 @@ #define MAX_TRIP_TEMP 205 /* This is the safest default Trip Temp value */ #define DEFAULT_TRIP_TEMP 50 +/* Trip Point Temp = (LTT / 2 - 50 degree C) */ #define GET_LTT_VALUE(x) (((x) + 50) * (2)) static uint8_t get_thermal_trip_temp(void) @@ -24,7 +25,6 @@ /* PCH Low Temp Threshold (LTT) */ static uint16_t pch_get_ltt_value(struct device *dev) { - uint16_t ltt_value; uint8_t thermal_config; thermal_config = get_thermal_trip_temp(); @@ -34,10 +34,7 @@ if (thermal_config > MAX_TRIP_TEMP) die("Input PCH temp trip is higher than allowed range!"); - /* Trip Point Temp = (LTT / 2 - 50 degree C) */ - ltt_value = GET_LTT_VALUE(thermal_config); - - return ltt_value; + return GET_LTT_VALUE(thermal_config); } /* Enable thermal sensor power management */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I791766bf2a78fa30dbba8cf4ad8a50e44f0e73ed Gerrit-Change-Number: 59309 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59209 to look at the new patch set (#7). Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... soc/intel/../thermal: Add support for thermal config behind PMC device Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/thermal.c 3 files changed, 125 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Raul Rangel (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56322 ) Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: ping -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Nov 2021 16:20:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload
by Raul Rangel (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58962 ) Change subject: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: ping -- To view, visit https://review.coreboot.org/c/coreboot/+/58962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Gerrit-Change-Number: 58962 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Nov 2021 16:20:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
by Raul Rangel (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58963 ) Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58963/comment/90894a51_b8d899f4 PS1, Line 9: This will enable preloading the microcode. > Why? Faster boot time? How much did it decrease? Done Patchset: PS2: ping -- To view, visit https://review.coreboot.org/c/coreboot/+/58963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Gerrit-Change-Number: 58963 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Nov 2021 16:18:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block: Add spi_hw mutex
by Raul Rangel (Code Review) 15 Nov '21

15 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58926 ) Change subject: soc/amd/common/block: Add spi_hw mutex ...................................................................... soc/amd/common/block: Add spi_hw mutex There are currently two users of the SPI hardware, the LPC SPI DMA controller, and the boot_device_rw device. We need to ensure exclusivity to the SPI hardware otherwise the SPI DMA controller can be interrupted and it will silently skip transferring some blocks. Depending on the SPI speed, this change might add a small delay when clearing the elog since a DMA transaction might be in flight. I'll continue optimizing the boot flow to avoid the delay. BUG=b:179699789 TEST=Hack up the code to interleave SPI transactions and verify this patch fixes the silent data corruption. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/lpc/spi_dma.c M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/common/block/spi/fch_spi_util.c 4 files changed, 27 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 35a3782..81da5dd 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_SPI_H #define AMD_BLOCK_SPI_H +#include <thread.h> #include <types.h> #define SPI_CNTRL0 0x00 @@ -118,4 +119,8 @@ void fch_spi_config_modes(void); void mainboard_spi_fast_speed_override(uint8_t *fast_speed); + +/* Ensure you hold the mutex when performing SPI transactions */ +extern struct thread_mutex spi_hw_mutex; + #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 5c69779..baf1eb8 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -122,6 +122,12 @@ ctrl |= LPC_ROM_DMA_CTRL_ERROR; /* Clear error */ ctrl |= LPC_ROM_DMA_CTRL_START; + /* + * Ensure we have exclusive access to the SPI controller before starting the LPC SPI DMA + * transaction. + */ + thread_mutex_lock(&spi_hw_mutex); + pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, ctrl); } @@ -135,6 +141,12 @@ if (spi_dma_is_busy()) return true; + /* + * Unlock the SPI mutex between DMA transactions to allow other users of the SPI + * controller to interleave their transactions. + */ + thread_mutex_unlock(&spi_hw_mutex); + if (spi_dma_has_error()) { printk(BIOS_ERR, "ERROR: SPI DMA failure: dest: %p, source: %#zx, size: %zu\n", diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 565fdbe..d95b642 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -142,7 +142,13 @@ static int xfer_vectors(const struct spi_slave *slave, struct spi_op vectors[], size_t count) { - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); + int rc; + + thread_mutex_lock(&spi_hw_mutex); + rc = spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); + thread_mutex_unlock(&spi_hw_mutex); + + return rc; } static int protect_a_range(u32 value) diff --git a/src/soc/amd/common/block/spi/fch_spi_util.c b/src/soc/amd/common/block/spi/fch_spi_util.c index 5cef565..862962f 100644 --- a/src/soc/amd/common/block/spi/fch_spi_util.c +++ b/src/soc/amd/common/block/spi/fch_spi_util.c @@ -6,6 +6,9 @@ #include <assert.h> #include <stdint.h> +/* Global SPI controller mutex */ +struct thread_mutex spi_hw_mutex; + static uintptr_t spi_base; void spi_set_base(void *base) -- To view, visit https://review.coreboot.org/c/coreboot/+/58926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Gerrit-Change-Number: 58926 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021