coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sudheer Amrabadi, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK ...................................................................... Patch Set 93: (2 comments) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133284): https://review.coreboot.org/c/coreboot/+/50586/comment/6f0babd0_ec8ca045 PS93, Line 533: while (1) suspect code indent for conditional statements (24, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133284): https://review.coreboot.org/c/coreboot/+/50586/comment/fde8fc58_fd4ea85d PS93, Line 554: while (1) suspect code indent for conditional statements (24, 24) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 93 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:13:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP soc: Added dram information to cbmem WIP
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: WIP soc: Added dram information to cbmem WIP ...................................................................... Patch Set 2: (80 comments) File src/soc/qualcomm/common/qclib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/8591cfda_7531ddf2 PS2, Line 27: #if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/4fd0c171_75b2a8aa PS2, Line 30: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/17acf1f3_bbde8d5f PS2, Line 31: uint64_t type; // enum that differentiates DDR3, LPDDR3, LPDDR4, etc. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/2bb5f632_81afb5c7 PS2, Line 32: uint64_t num_channels; // To know how may channels are available. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/287e44d1_bbfea43e PS2, Line 33: uint64_t reserved[6]; // Reserved [6] please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/80f5d1b0_94092727 PS2, Line 34: struct please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/db40eddb_e5571a3e PS2, Line 35: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/40cb2cbc_07a85489 PS2, Line 35: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/83676043_19eff9ea PS2, Line 36: uint64_t density; // Total density Seen on channel code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/856c0e05_511e4a93 PS2, Line 36: uint64_t density; // Total density Seen on channel please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/e0cef13a_4731d107 PS2, Line 37: uint64_t io_width; // JEDEC MR8 - io width code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/1c257380_2180a3cd PS2, Line 37: uint64_t io_width; // JEDEC MR8 - io width please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/f65ae283_04a6033a PS2, Line 38: uint64_t manufacturer_id; // JEDEC MR5 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/647567a3_7d54e0ae PS2, Line 38: uint64_t manufacturer_id; // JEDEC MR5 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/2868e474_6cd4b44b PS2, Line 39: uint64_t revision_id[2]; // JEDEC MR6, MR7 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c8eea3db_cf42b4cc PS2, Line 39: uint64_t revision_id[2]; // JEDEC MR6, MR7 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/31c8bc0b_2928a820 PS2, Line 40: uint64_t reserved[4]; // Reserved code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/0843faf7_ad7ffb7c PS2, Line 40: uint64_t reserved[4]; // Reserved please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/a5581404_f01a5da3 PS2, Line 41: uint64_t serial_id[8]; // for potential future LPDDR5 expansion code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/027a98c6_1fbc16c4 PS2, Line 41: uint64_t serial_id[8]; // for potential future LPDDR5 expansion please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/5773efde_cdadba0f PS2, Line 42: } channels[DDR_MAX_NUM_CH_TEST]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/7183f135_acde82f8 PS2, Line 43: }dram_info; space required after that close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/f09edbb6_ca4dc683 PS2, Line 48: /* Save MEM CHIP info in SRAM region to share with ramstage */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/cad80945_4087ca6f PS2, Line 49: mem_chip_offset = (void *)te->blob_address; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/7d23799e_b5cf85ba PS2, Line 49: mem_chip_offset = (void *)te->blob_address; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/bd8acddc_129725b4 PS2, Line 50: mem_chip_size = te->size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/1529f6d6_d1faee7a PS2, Line 50: mem_chip_size = te->size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/89a480b5_f00b4add PS2, Line 55: printk(BIOS_INFO, "%s:%s: Test Code to print memchip information before adding cbmem_add\n", __FILE__, __func__); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/3e39b222_8c249c80 PS2, Line 56: memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/1ff5960f_0c126559 PS2, Line 56: memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/a7c3bf11_4132a91e PS2, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/a234594e_f1596b4d PS2, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/490eec6f_eba3db61 PS2, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/d8ef73bb_77d71124 PS2, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/8445ffc5_53667ccc PS2, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/785a14e0_51a80f5c PS2, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/0304b850_9fde2967 PS2, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/deff6822_be2ea76a PS2, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/44f88495_042549e9 PS2, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c6c05b1a_24ae9382 PS2, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/df951351_acaaa2a4 PS2, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/47a106ca_a4c800ec PS2, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/bf58f44b_cb1be2ed PS2, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/881a8aea_4d7d668b PS2, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/9c35acae_183021e1 PS2, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/ab24ae3a_396e3822 PS2, Line 66: void *mem_region_base; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/3acfd9c2_32a3361b PS2, Line 66: void *mem_region_base; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/a424534d_afcffcaa PS2, Line 69: mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c11cc514_3e5bcf2a PS2, Line 69: mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/28771d8b_53a36993 PS2, Line 70: ASSERT(mem_region_base != NULL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/90af379e_556c71b5 PS2, Line 70: ASSERT(mem_region_base != NULL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/b40c5fe7_772a81b0 PS2, Line 72: /* Migrate the data into CBMEM */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c6ac043c_8b3cb947 PS2, Line 73: memcpy(mem_region_base, mem_chip_offset, mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/811e4837_ecb2c324 PS2, Line 73: memcpy(mem_region_base, mem_chip_offset, mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/18459180_f70966fd PS2, Line 77: /* Test Code to print memchip information after adding cbmem_addd */ 'addd' may be misspelled - perhaps 'add'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c978cb73_96bf2a0b PS2, Line 78: printk(BIOS_INFO, "%s:%s: Test Code to print memchip information after adding cbmem_add\n", __FILE__, __func__); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/69d2d084_019a146f PS2, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/1b296d14_1c598fde PS2, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/7d440376_ac396a97 PS2, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/e247d27c_38e681da PS2, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); space prohibited before that ',' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/a9dc4184_a04ba6ea PS2, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/6ac9f11c_b47680ef PS2, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/aab98c14_df7bb38a PS2, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c39805c5_8ecaaf5b PS2, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/2a7302ae_64d78f3e PS2, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/418445c2_bd4e3675 PS2, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/ac352b09_db354290 PS2, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/95f88d59_698c7a0b PS2, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/77124c7c_0303c69d PS2, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/f787a8a7_dea8c58a PS2, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/69826f81_2cf017bf PS2, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/0cc9af16_9c9b277c PS2, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/4aea9239_54a42745 PS2, Line 157: sizeof(te->name))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/2b558f78_72d5a06b PS2, Line 157: sizeof(te->name))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/c8be6157_06e85bc0 PS2, Line 158: write_mem_chip_information(te); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/55c45b62_3ba88377 PS2, Line 158: write_mem_chip_information(te); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/9669dec2_fb23047d PS2, Line 213: qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/f364a41d_aa9f5dfc PS2, Line 213: qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/b0bd7f79_5c8a23be PS2, Line 214: _mem_chip_info, REGION_SIZE(mem_chip_info), 0); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133282): https://review.coreboot.org/c/coreboot/+/59195/comment/49bac46c_1894c9c8 PS2, Line 214: _mem_chip_info, REGION_SIZE(mem_chip_info), 0); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:12:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP libpayload: Parse DDR Information through coreboot tables WIP
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: WIP libpayload: Parse DDR Information through coreboot tables WIP ...................................................................... Patch Set 2: (4 comments) File payloads/libpayload/libc/coreboot.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/ff44e7fd_d4393b75 PS2, Line 357: cb_parse_mem_chip_info(ptr, info); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/8104485c_6152b84d PS2, Line 357: cb_parse_mem_chip_info(ptr, info); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/c33b4781_92700611 PS2, Line 358: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133280): https://review.coreboot.org/c/coreboot/+/59193/comment/25060187_1b0b385c PS2, Line 358: break; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:11:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage
by Rob Barnes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 ) Change subject: soc/amd/cezanne/romstage: Call preload_ramstage ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93ae358986059cdae6069421f4efba586235df51 Gerrit-Change-Number: 58983 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:10:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... Patch Set 7: (1 comment) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133277): https://review.coreboot.org/c/coreboot/+/58545/comment/77264f8f_6bd3b652 PS7, Line 27: if (soc_modem_carve_out(&start, &end)) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 7 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:10:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/lib/prog_loaders: Add preload_ramstage
by Rob Barnes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Raul Rangel, Martin Roth, Julius Werner. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58982 ) Change subject: src/lib/prog_loaders: Add preload_ramstage ...................................................................... Patch Set 3: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/58982/comment/617d7bb1_5e624581 PS3, Line 1219: $(CONFIG_CBFS_PREFIX)/ramstage-align := 64 Should there be an else block here? i.e. what is ramstage-align when CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA=n? -- To view, visit https://review.coreboot.org/c/coreboot/+/58982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 Gerrit-Change-Number: 58982 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:09:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56093 ) Change subject: mb/google/herobrine: Initialize USB by calling SOC method ...................................................................... Patch Set 37: (3 comments) File src/mainboard/google/herobrine/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133271): https://review.coreboot.org/c/coreboot/+/56093/comment/90194833_826c954d PS37, Line 19: .parameter_override_x0 = 0xe6, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133271): https://review.coreboot.org/c/coreboot/+/56093/comment/6d7a034d_12f03283 PS37, Line 20: .parameter_override_x1 = 0x8b, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133271): https://review.coreboot.org/c/coreboot/+/56093/comment/ef913def_07ca512b PS37, Line 21: .parameter_override_x2 = 0x16, please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/56093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Gerrit-Change-Number: 56093 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 15:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: Initialize USB by calling SOC method
by Ravi kumar (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56093 to look at the new patch set (#37). Change subject: mb/google/herobrine: Initialize USB by calling SOC method ...................................................................... mb/google/herobrine: Initialize USB by calling SOC method Initialize by calling `setup_usb_host0()` from SOC code BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 --- M src/mainboard/google/herobrine/mainboard.c M src/mainboard/google/herobrine/romstage.c 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56093/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/56093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2 Gerrit-Change-Number: 56093 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: Add support for USB
by Ravi kumar (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Sandeep Maheswaram, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56092 to look at the new patch set (#37). Change subject: sc7280: Add support for USB ...................................................................... sc7280: Add support for USB Adding USB addressmap for sc7280. Use common USB driver for sc7280. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/include/soc/addressmap.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/56092/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/56092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 Gerrit-Change-Number: 56092 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Ravi kumar (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56091 to look at the new patch set (#37). Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... soc/qualcomm/common/usb: Add support for common USB driver Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 --- M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/usb_common.h R src/soc/qualcomm/common/usb/qmpv3_usb_phy.c A src/soc/qualcomm/common/usb/qmpv4_usb_phy.c A src/soc/qualcomm/common/usb/qusb_phy.c A src/soc/qualcomm/common/usb/snps_usb_phy.c A src/soc/qualcomm/common/usb/usb.c M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/include/soc/usb.h 13 files changed, 1,028 insertions(+), 416 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021