coreboot-gerrit November 2021

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Change in coreboot[master]: qualcomm/sc7280: gpio: Support eGPIO scheme
by Ravi kumar (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Taniya Das, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58580 to look at the new patch set (#6). Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme ...................................................................... qualcomm/sc7280: gpio: Support eGPIO scheme eGPIO is a scheme which allows special power island domain IOs to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. Allow the eGPIO to be configured via gpio_configure API to be used as a TLMM gpio. Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 --- M src/soc/qualcomm/common/gpio.c M src/soc/qualcomm/common/include/soc/gpio_common.h 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58580/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/58580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 Gerrit-Change-Number: 58580 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by Ravi kumar (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ravi kumar. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49768 to look at the new patch set (#89). Change subject: sc7280: Add CPUCP firmware support ...................................................................... sc7280: Add CPUCP firmware support CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/cpucp_load_reset.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/cpucp.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 7 files changed, 101 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49768/89 -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 89 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/hardwaremain: Run timers more frequently
by Rob Barnes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Raul Rangel, Julius Werner, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58955 ) Change subject: lib/hardwaremain: Run timers more frequently ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8 Gerrit-Change-Number: 58955 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 14:55:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_rom: Add vga_oprom_preload
by Rob Barnes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56581 ) Change subject: device/pci_rom: Add vga_oprom_preload ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549 Gerrit-Change-Number: 56581 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 14:53:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Update SPKR GPIO configuration
by Rob Barnes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Kevin Chiu, Bhanu Prakash Maiya, Eric Peers, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59051 ) Change subject: mb/google/guybrush/var/nipperkin: Update SPKR GPIO configuration ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/59051/comment/98747215_d2731f3e PS4, Line 70: PAD_NC(GPIO_31), Guybrush reference board v2 still uses GPIO_31 for EN_SPKR. So this needs to be overridden there. -- To view, visit https://review.coreboot.org/c/coreboot/+/59051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Gerrit-Change-Number: 59051 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 14:28:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Usha P (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Usha P. Usha P has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Usha P (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Usha P. Usha P has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Subrata Banik (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Tim Wawrzynczak, Usha P, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/alderlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/59306/comment/0b597532_97046486 PS1, Line 30: -N may be make it as "Alderlake" alone like other does without additional overhead ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 14:07:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Usha P (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 13:58:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alder Lake device IDs
by Usha P (Code Review) 15 Nov '21

15 Nov '21

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59306 ) Change subject: soc/intel/common: Include Alder Lake device IDs ...................................................................... soc/intel/common: Include Alder Lake device IDs Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/59306/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 5314076..0f7c5c1 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -55,5 +55,6 @@ #define CPUID_ALDERLAKE_A1 0x906a1 #define CPUID_ALDERLAKE_A2 0x906a2 #define CPUID_ALDERLAKE_A3 0x906a4 +#define CPUID_ALDERLAKE_N_A0 0xb06e0 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c6ef121..e17eea4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3885,6 +3885,8 @@ #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa #define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT1 0x46A0 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT2 0x46A3 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3994,6 +3996,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f #define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B + /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2fc8eab..cec4db7 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -27,6 +27,7 @@ { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, }; static struct { @@ -43,6 +44,8 @@ { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, "Alderlake-M" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" }, }; static struct { @@ -111,6 +114,8 @@ { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index acd15a8..b7e2243 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -72,6 +72,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0}, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e7e96ad..2a8a076 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -311,6 +311,8 @@ PCI_DEVICE_ID_INTEL_ADL_M_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT2, PCI_DEVICE_ID_INTEL_ADL_M_GT3, + PCI_DEVICE_ID_INTEL_ADL_N_GT1, + PCI_DEVICE_ID_INTEL_ADL_N_GT2, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 45e1d42..56ee6a4 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -433,6 +433,8 @@ PCI_DEVICE_ID_INTEL_ADL_P_ID_9, PCI_DEVICE_ID_INTEL_ADL_M_ID_1, PCI_DEVICE_ID_INTEL_ADL_M_ID_2, + PCI_DEVICE_ID_INTEL_ADL_N_ID_1, + PCI_DEVICE_ID_INTEL_ADL_N_ID_2, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Gerrit-Change-Number: 59306 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021