coreboot-gerrit November 2021

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Change in coreboot[master]: mb/siemens/mc_ehl: Disable HECI #2 device
by Felix Held (Code Review) 15 Nov '21

15 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58940 ) Change subject: mb/siemens/mc_ehl: Disable HECI #2 device ...................................................................... mb/siemens/mc_ehl: Disable HECI #2 device HECI #2 is not used for CSE communication. Therefore, it is not necessary to set the parameter 'Heci2Enable' in devicetree. Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index e96e654..228bf60 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -18,7 +18,6 @@ # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "Heci2Enable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 67ff3d0..39789be 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -18,7 +18,6 @@ # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "Heci2Enable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/58940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9 Gerrit-Change-Number: 58940 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Sridhar Siricilla (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55364 ) Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... Patch Set 10: (4 comments) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/55364/comment/94c8ddd5_e31d3dc5 PS3, Line 132: Dependendcy :CSE > ` :` → `: ` Done https://review.coreboot.org/c/coreboot/+/55364/comment/6020a1b8_40867d22 PS3, Line 132: Dependendcy > Dependency Done https://review.coreboot.org/c/coreboot/+/55364/comment/df7f32cc_ca3ec638 PS3, Line 132: Init > initialization Done https://review.coreboot.org/c/coreboot/+/55364/comment/46ce82c6_8947f495 PS3, Line 133: if (!s3wake) { : if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) > e.g. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 10:51:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
by Sridhar Siricilla (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Paul Menzel, Ravindra, Patrick Rudolph. Hello build bot (Jenkins), Sridhar Siricilla, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55364 to look at the new patch set (#10). Change subject: soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init ...................................................................... soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init The patch enables cse_fw_sync() before DRAM initialization. BUG=b:175516533 TEST=Dependency with CSE Litev16.0.15.1545 integration Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55364/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/55364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d Gerrit-Change-Number: 55364 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons
by Felix Singer (Code Review) 15 Nov '21

15 Nov '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59191 ) Change subject: soc/intel/alderlake: Disable VT-d for early silicons ...................................................................... soc/intel/alderlake: Disable VT-d for early silicons VT-d needs to disabled for early silicons as it results in a CPU hard hang. BUG=b:197177091 Test=Boot brya to OS with no hang Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index be71a02..121251e 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -3,6 +3,7 @@ #include <assert.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/intel/cpu_ids.h> #include <device/device.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -259,6 +260,14 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + const uint32_t cpuid = cpu_get_cpuid(); + + /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ + if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) { + m_cfg->VtdDisable = 1; + return; + } + m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/59191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Gerrit-Change-Number: 59191 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/drivers: Add notes on Realtek HW EQ
by Sean Rhodes (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Matt DeVillier, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59263 ) Change subject: Documentation/drivers: Add notes on Realtek HW EQ ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/59263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie13f62622a4cf2b14d36728a8a4a9e3ef24d6852 Gerrit-Change-Number: 59263 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 10:23:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
by 9elements QA (Code Review) 15 Nov '21

15 Nov '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59013 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 3 / 1 / 4 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/82158 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/82157 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/82156 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/82155 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/59013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Gerrit-Change-Number: 59013 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 10:21:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Correct SSD power sequence
by Casper Chang (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Ariel Fang, Malik Hsu, Tim Wawrzynczak. Hello Ariel Fang, Malik Hsu, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59303 to look at the new patch set (#2). Change subject: mb/google/brya/variants/primus: Correct SSD power sequence ...................................................................... mb/google/brya/variants/primus: Correct SSD power sequence SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199967106 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 --- M src/mainboard/google/brya/variants/primus/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59303/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Gerrit-Change-Number: 59303 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/primus: Correct SSD power sequence
by Casper Chang (Code Review) 15 Nov '21

15 Nov '21

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59303 ) Change subject: mb/google/primus: Correct SSD power sequence ...................................................................... mb/google/primus: Correct SSD power sequence SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199967106 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 --- M src/mainboard/google/brya/variants/primus/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/59303/1 diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index c1dfee2..4c9434e 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -80,6 +80,8 @@ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -117,16 +119,13 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), - /* B4 : PROC_GP3 ==> SSD_PERST_L - * SSD_PERST_L is released after EN_PP3300_SSD is asserted; the - * power rails take some time to come up. - */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7 Gerrit-Change-Number: 59303 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Create beadrix variant
by Teddy Shih (Code Review) 15 Nov '21

15 Nov '21

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59302 ) Change subject: mb/google/dedede: Create beadrix variant ...................................................................... mb/google/dedede: Create beadrix variant Create the beadrix variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:204882915 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BEADRIX Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h A src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h A src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc A src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/beadrix/overridetree.cb 8 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/59302/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 64fca47..29a9481 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -111,6 +111,7 @@ default "Corori" if BOARD_GOOGLE_CORORI default "Driblee" if BOARD_GOOGLE_DRIBLEE default "Gooey" if BOARD_GOOGLE_GOOEY + default "Beadrix" if BOARD_GOOGLE_BEADRIX config MAX_CPUS int @@ -148,6 +149,7 @@ default "corori" if BOARD_GOOGLE_CORORI default "driblee" if BOARD_GOOGLE_DRIBLEE default "gooey" if BOARD_GOOGLE_GOOEY + default "beadrix" if BOARD_GOOGLE_BEADRIX endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 78b9fd5..9b71280 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -169,3 +169,8 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 select BASEBOARD_DEDEDE_LAPTOP select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + +config BOARD_GOOGLE_BEADRIX + bool "-> Beadrix" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h b/src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h b/src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc new file mode 100644 index 0000000..6751a42 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb new file mode 100644 index 0000000..404024b --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/59302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6 Gerrit-Change-Number: 59302 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/felwinter: Disable PCIE port 6
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59243 ) Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6 ...................................................................... mb/google/brya/var/felwinter: Disable PCIE port 6 PCIE port 6 is empty as per schematics. BUG=b:206047996 TEST=PCIE port 6 is disabled. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index dedd192..5b90b9a 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -60,6 +60,7 @@ end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30fa897c9310c44545e3df670895639a5144e1de Gerrit-Change-Number: 59243 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021