coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/felwinter: Remove USB2 port 0
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59236 ) Change subject: mb/google/brya/var/felwinter: Remove USB2 port 0 ...................................................................... mb/google/brya/var/felwinter: Remove USB2 port 0 USB2 port 0 is empty as per schematics. BUG=b:206047996 TEST=USB2 port 0 is disabled. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 8420452..dedd192 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -15,6 +15,7 @@ .configure_ext_fivr = 1, }" + register "usb2_ports[0]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_EMPTY" 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403 Gerrit-Change-Number: 59236 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/felwinter: Enable garage pen detection
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59234 ) Change subject: mb/google/brya/var/felwinter: Enable garage pen detection ...................................................................... mb/google/brya/var/felwinter: Enable garage pen detection Enable garage pen detection. BUG=b:197912223 TEST=Check evtest can trigger event when toggling the switch. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib5929c876d1a0da34dadd7997a61ab8e75acbbb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59234 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/felwinter/overridetree.cb 2 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bd8cf6f..4afee74 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -60,6 +60,7 @@ config BOARD_GOOGLE_FELWINTER bool "-> Felwinter" select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENERIC_GPIO_KEYS config BOARD_GOOGLE_ANAHERA bool "-> Anahera" diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 4647551..8420452 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -101,6 +101,18 @@ register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A7)" + register "key.wake_gpe" = "GPE0_DW0_08" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end device ref i2c3 on end device ref i2c5 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5929c876d1a0da34dadd7997a61ab8e75acbbb6 Gerrit-Change-Number: 59234 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Set soc name for Stoneyridge
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58555 ) Change subject: amdfwtool: Set soc name for Stoneyridge ...................................................................... amdfwtool: Set soc name for Stoneyridge For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 9 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index fd3ebf7..d265651 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -123,6 +123,7 @@ ifeq ($(FIRMWARE_TYPE),ST) OPT_COMBOCAPABLE=--combo-capable +OPT_SOCNAME=--soc-name "Stoneyridge" endif ifeq ($(CONFIG_USE_PSPSECUREOS),y) @@ -147,6 +148,7 @@ $(OPT_COMBOCAPABLE)\ $(OPT_PSP_USE_PSPSECUREOS) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ + $(OPT_SOCNAME) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index b10315e..ee360f0 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1586,11 +1586,13 @@ amd_romsig->xhci_entry = 0; if (soc_id != PLATFORM_UNKNOWN) { - retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, - efs_spi_speed, efs_spi_micron_flag); - if (retval) { - fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); - return retval; + if (soc_id != PLATFORM_STONEYRIDGE) { + retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, + efs_spi_speed, efs_spi_micron_flag); + if (retval) { + fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); + return retval; + } } } else { fprintf(stderr, "WARNING: No SOC name specified.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/58555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Gerrit-Change-Number: 58555 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/stoneyridge/include/pci_devs: remove unused DEVID defines
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59268 ) Change subject: soc/amd/stoneyridge/include/pci_devs: remove unused DEVID defines ...................................................................... soc/amd/stoneyridge/include/pci_devs: remove unused DEVID defines None of the *_DEVID defines was used in the code, so drop those. The SoC code uses the PCI ID defines from include/device/pci_ids.h instead. Since it might still be useful to have the PCI device IDs as a reference in the SoC's pci_devs.h, add those as comments instead. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59268 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/pci_devs.h 1 file changed, 21 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 6af657f..4e5c8fc 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -6,17 +6,15 @@ #include <device/pci_def.h> #include <amdblocks/pci_devs.h> -/* GNB Root Complex */ +/* GNB Root Complex: GNB_DEVID 0x1576 */ #define GNB_DEV 0x0 #define GNB_FUNC 0 -#define GNB_DEVID 0x1576 #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) #define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) -/* IOMMU */ +/* IOMMU: IOMMU_DEVID 0x1577 */ #define IOMMU_DEV 0x0 #define IOMMU_FUNC 2 -#define IOMMU_DEVID 0x1577 #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) @@ -41,59 +39,51 @@ #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) -/* Host Bridge */ +/* Host Bridge: HOST_DEVID 0x157b */ #define HOST_DEV 0x2 #define HOST_FUNC 0 -#define HOST_DEVID 0x157b #define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC) #define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC) -/* PCIe GPP Bridge 0 */ +/* PCIe GPP Bridge 0: PCIE0_DEVID 0x157c */ #define PCIE0_DEV 0x2 #define PCIE0_FUNC 1 -#define PCIE0_DEVID 0x157c #define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC) #define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC) -/* PCIe GPP Bridge 1 */ +/* PCIe GPP Bridge 1: PCIE1_DEVID 0x157c */ #define PCIE1_DEV 0x2 #define PCIE1_FUNC 2 -#define PCIE1_DEVID 0x157c #define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC) #define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC) -/* PCIe GPP Bridge 2 */ +/* PCIe GPP Bridge 2: PCIE2_DEVID 0x157c */ #define PCIE2_DEV 0x2 #define PCIE2_FUNC 3 -#define PCIE2_DEVID 0x157c #define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC) #define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC) -/* PCIe GPP Bridge 3 */ +/* PCIe GPP Bridge 3: PCIE3_DEVID 0x157c */ #define PCIE3_DEV 0x2 #define PCIE3_FUNC 4 -#define PCIE3_DEVID 0x157c #define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC) #define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC) -/* PCIe GPP Bridge 4 */ +/* PCIe GPP Bridge 4: PCIE4_DEVID 0x157c */ #define PCIE4_DEV 0x2 #define PCIE4_FUNC 5 -#define PCIE4_DEVID 0x157c #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) #define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) -/* Platform Security Processor */ +/* Platform Security Processor: PSP_DEVID 0x1578 */ #define PSP_DEV 0x8 #define PSP_FUNC 0 -#define PSP_DEVID 0x1578 #define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) #define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) -/* HD Audio 1 */ +/* HD Audio 1: HDA1_DEVID 0x157a */ #define HDA1_DEV 0x9 #define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) @@ -157,47 +147,44 @@ #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) -/* XHCI */ +/* XHCI: XHCI_DEVID 0x7914 */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x7914 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) -/* SATA */ +/* + * SATA: + * SATA_IDE_IDEVID 0x7900 + * AHCI_DEVID_MS 0x7901 + * AHCI_DEVID_AMD 0x7904 + */ #define SATA_DEV 0x11 #define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) -/* EHCI */ +/* EHCI: EHCI_DEVID 0x7908 */ #define EHCI_DEV 0x12 #define EHCI_FUNC 0 -#define EHCI_DEVID 0x7908 #define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) #define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) -/* SMBUS */ +/* SMBUS: SMBUS_DEVID 0x790b */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x790b #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) -/* LPC BUS */ +/* LPC BUS: LPC_DEVID 0x790e */ #define PCU_DEV 0x14 #define LPC_FUNC 3 -#define LPC_DEVID 0x790e #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -/* SD Controller */ +/* SD Controller: SD_DEVID 0x7906 */ #define SD_DEV 0x14 #define SD_FUNC 7 -#define SD_DEVID 0x7906 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -- To view, visit https://review.coreboot.org/c/coreboot/+/59268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b Gerrit-Change-Number: 59268 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59135 ) Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge ...................................................................... mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less than 1, do not enable RTD3 driver. BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/Makefile.inc M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus/overridetree.cb A src/mainboard/google/brya/variants/primus/variant.c 4 files changed, 28 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/Makefile.inc b/src/mainboard/google/brya/variants/primus/Makefile.inc index 129a293..725b883 100644 --- a/src/mainboard/google/brya/variants/primus/Makefile.inc +++ b/src/mainboard/google/brya/variants/primus/Makefile.inc @@ -3,3 +3,4 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index c1dfee2..a324fa3 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -45,8 +45,6 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), - /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ - PAD_CFG_GPO(GPP_E20, 1, DEEP), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), @@ -107,6 +105,8 @@ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ PAD_CFG_GPO(GPP_F21, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 81dc1c0..8028798 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -128,6 +128,11 @@ end end device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "srcclk_pin" = "6" + device generic 0 alias emmc_rtd3 on end + end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 6, diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c new file mode 100644 index 0000000..4780334 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> + +static void devtree_update_emmc_rtd3(uint32_t board_ver) +{ + struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3); + if (board_ver > 1) + return; + + emmc_rtd3->enabled = 0; +} + +void variant_devtree_update(void) +{ + uint32_t board_ver = board_id(); + devtree_update_emmc_rtd3(board_ver); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Gerrit-Change-Number: 59135 Gerrit-PatchSet: 7 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/wifi/generic: fix package_size to align with WLAN driver
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58951 ) Change subject: drivers/wifi/generic: fix package_size to align with WLAN driver ...................................................................... drivers/wifi/generic: fix package_size to align with WLAN driver Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3 no matter what the revision is for EWRD. It will pass the WLAN driver check then to retrieve the data properly. BUG=b:204414616 TEST= tested on brya with DRTU tool to verify if SAR table is read properly or not. Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Signed-off-by: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Kane Chen: Looks good to me, but someone else must approve diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 11fc0e0..3cc1c63 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -273,7 +273,7 @@ * Emit 'Domain Type' + 'Dynamic SAR Enable' + 'Extended SAR sets count' * + number of bytes for Set#2 & 3 & 4 */ - package_size = 1 + 1 + 1 + table_size * sar->dsar_set_count; + package_size = 1 + 1 + 1 + table_size * MAX_DSAR_SET_COUNT; acpigen_write_package(package_size); acpigen_write_dword(DOMAIN_TYPE_WIFI); acpigen_write_dword(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/58951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Gerrit-Change-Number: 58951 Gerrit-PatchSet: 7 Gerrit-Owner: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/gimble: Update PL1 min value
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58650 ) Change subject: mb/google/brya/variants/gimble: Update PL1 min value ...................................................................... mb/google/brya/variants/gimble: Update PL1 min value Update PL1 minimum value from 3W to 12W as per the thermal design discussed in this bug 203371203 comment #10. BUG=b:203371203 BRANCH=None TEST=Build and boot the gimble system Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58650 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Scott Chao: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 842dd00..1a4277f 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -63,7 +63,7 @@ }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, + .min_power = 12000, .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/58650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46 Gerrit-Change-Number: 58650 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-CC: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: neha1.kumari(a)intel.com Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59013 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 The headers added are generated as per FSP v2422_01. Previous FSP version was v2374_01. Changes Include: - Add CnviDdrRfim UPD in FspmUpd.h - UPDs description update in FspmUpd.h BUG=b:205512463 BRANCH=None TEST=Build and boot brya Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59013 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h 1 file changed, 28 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 9e1a414..271e01c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -454,10 +454,10 @@ UINT8 ApertureSize; /** Offset 0x01D0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC - DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 2:Desktop 2DPC DDR5, 5:ULT/ULX/Mobile Halo - Type3, 6:ULT/ULX/Mobile Halo Type4, 8:UP Server + MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server + 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server **/ UINT8 UserBd; @@ -474,7 +474,7 @@ /** Offset 0x01D4 - SA GV System Agent dynamic frequency support and when enabled memory will be training - at three different frequencies. + at four different frequencies. 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled **/ UINT8 SaGv; @@ -1966,9 +1966,11 @@ **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x080D - Reserved +/** Offset 0x080D - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS **/ - UINT8 Reserved27; + UINT8 CnviDdrRfim; /** Offset 0x080E - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1991,7 +1993,7 @@ /** Offset 0x0811 - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved27[3]; /** Offset 0x0814 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -2019,7 +2021,7 @@ /** Offset 0x081B - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved28; /** Offset 0x081C - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2339,7 +2341,7 @@ /** Offset 0x0854 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x0855 - Extern Therm Status Enables/Disable Extern Therm Status @@ -2379,7 +2381,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x085C - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2485,7 +2487,7 @@ /** Offset 0x086D - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved31[2]; /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2544,7 +2546,7 @@ /** Offset 0x087E - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) @@ -2754,7 +2756,7 @@ /** Offset 0x08A8 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x08AA - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2786,7 +2788,7 @@ /** Offset 0x08AF - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved34; /** Offset 0x08B0 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2860,7 +2862,7 @@ /** Offset 0x08BB - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x08BC - Post Code Output Port This option configures Post Code Output Port @@ -2887,7 +2889,7 @@ /** Offset 0x08C1 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x08C4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No @@ -2937,7 +2939,7 @@ /** Offset 0x08DB - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x08DE - REFRESH_PANIC_WM DEPRECATED @@ -2963,7 +2965,7 @@ /** Offset 0x08E2 - Reserved **/ - UINT8 Reserved39[9]; + UINT8 Reserved38[9]; /** Offset 0x08EB - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2986,7 +2988,7 @@ /** Offset 0x08EE - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved39; /** Offset 0x08EF - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -3003,7 +3005,7 @@ /** Offset 0x08F1 - Reserved **/ - UINT8 Reserved41[3]; + UINT8 Reserved40[3]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3017,7 +3019,7 @@ /** Offset 0x08F9 - Reserved **/ - UINT8 Reserved42[95]; + UINT8 Reserved41[95]; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3033,7 +3035,7 @@ /** Offset 0x095C - Reserved **/ - UINT8 Reserved43[12]; + UINT8 Reserved42[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3099,7 +3101,7 @@ /** Offset 0x0972 - Reserved **/ - UINT8 Reserved44[2]; + UINT8 Reserved43[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3136,7 +3138,7 @@ /** Offset 0x0A97 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved44; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3162,7 +3164,7 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved46[104]; + UINT8 Reserved45[104]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/59013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id25f7199ffd08a4a74585ea1269d927efa733b8c Gerrit-Change-Number: 59013 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: Add thermal sensor settings
by Werner Zeh (Code Review) 15 Nov '21

15 Nov '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59089 ) Change subject: mb/google/brya/var/kano: Add thermal sensor settings ...................................................................... mb/google/brya/var/kano: Add thermal sensor settings Kano has 3 thermal sensors, so add the missing sensor settings. BUG=b:205648035 TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 8aca8b4..499dad2 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -49,7 +49,8 @@ chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" # TODO: below values are initial reference values only ## Active Policy @@ -68,7 +69,8 @@ register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), }" ## Critical Policy @@ -76,6 +78,7 @@ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), }" register "controls.power_limits" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/59089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412 Gerrit-Change-Number: 59089 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Hook up two missing sensors
by Wisley Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Chen Wisley, Paul Menzel. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58970 ) Change subject: mb/google/brya/var/redrix: Hook up two missing sensors ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/redrix/overridetree.cb: https://review.coreboot.org/c/coreboot/+/58970/comment/bdafbc1f_86fa0212 PS1, Line 88: register "options.tsr[2].desc" = ""Charger"" > yes. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/58970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603 Gerrit-Change-Number: 58970 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 15 Nov 2021 09:38:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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