coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/brya/var/vell: update overridetree
by Kevin Chiu (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Kevin Chiu. Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59304 to review the following change. Change subject: mb/google/brya/var/vell: update overridetree ...................................................................... mb/google/brya/var/vell: update overridetree BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/vell/overridetree.cb 2 files changed, 372 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/59304/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 4afee74..2c088c3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -71,4 +71,7 @@ config BOARD_GOOGLE_VELL bool "-> Vell" - select BOARD_GOOGLE_BASEBOARD_BRYA + select BOARD_GOOGLE_BASEBOARD_BRY + select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GFX_GENERIC + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 4f2c04a..7d003b3 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -1,6 +1,371 @@ +fw_config + field DB_SD 0 1 + option SD_ABSENT 0 + option SD_GL9750 1 + end + field KB_BL 2 2 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 3 5 + option AUDIO_UNKNOWN 0 + option MAX98360_ALC5682I_I2S 1 + option MAX98360_ALC5682IVS_I2S 2 + end + field DB_LTE 6 7 + option LTE_ABSENT 0 + option LTE_USB 1 + end + field EPS 10 10 + option PRIVACY_SCREEN_ABSENT 0 + option PRIVACY_SCREEN 1 + end +end chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" - device domain 0 on - end - + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)" + device generic 0 on + probe EPS PRIVACY_SCREEN + end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""Regulator"" + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp6 off end + device ref pcie_rp7 on + # Enable PCIE eMMC bridge 7 using clk 6 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + end #PCIE7 EMMC + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682IVS_I2S + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + register "stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa910eb1c5584197907963781258035c668298e Gerrit-Change-Number: 59304 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Attention: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/drivers: Add notes on Realtek HW EQ
by Angel Pons (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Sean Rhodes, Matt DeVillier, Angel Pons. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59263 ) Change subject: Documentation/drivers: Add notes on Realtek HW EQ ...................................................................... Patch Set 4: Code-Review+1 (10 comments) Patchset: PS4: Thank you so much! File Documentation/drivers/realtek.md: https://review.coreboot.org/c/coreboot/+/59263/comment/92f02438_ac10b5ef PS4, Line 4: The datasheet has extensive documentation on this, as after : it says that it supports it, it provides all the below information on : how to configure it: : : ``` : : ``` : As this information is extemely helpful, we wrote up the notes below on : how to configure it. While I appreciate the sense of humour, I'm not sure if everyone would understand the sarcasm here. Maybe dilute it a bit? The Realtek ALC256 and several other codecs support a 7-band hardware equalizer. The datasheet clearly and earnestly encourages its readers to harness the entire potential of this hardware feature by providing absolutely no information on how to configure it. https://review.coreboot.org/c/coreboot/+/59263/comment/8134c5e8_1cce98d1 PS4, Line 12: mamed typo? ma*i*med https://review.coreboot.org/c/coreboot/+/59263/comment/3294e7a9_b6559f65 PS4, Line 13: killed Rest in pieces 😭 https://review.coreboot.org/c/coreboot/+/59263/comment/54ad4616_ef0b0b5a PS4, Line 19: 53 0x53, actually. Same for all other values. https://review.coreboot.org/c/coreboot/+/59263/comment/c4f93e4f_0c11eb1b PS4, Line 28: 0x053404DA nit: Hex values in coreboot are typically written in lowercase https://review.coreboot.org/c/coreboot/+/59263/comment/a9f37dda_60333638 PS4, Line 41: Butterworth HPF Butterworth High-Pass Filter? Maybe link to Wikipedia? https://en.wikipedia.org/wiki/Butterworth_filter https://review.coreboot.org/c/coreboot/+/59263/comment/00227485_dc298c33 PS4, Line 136: trailing space https://review.coreboot.org/c/coreboot/+/59263/comment/631b9228_15f056b8 PS4, Line 136: /* : * EQ Mode = Boost Gain : * : * High Pass Filter 1: : * Band Width = 1000Hz : * Gain (dB) = 0dB : * : * High Pass Filter 2: : * Band Width = 1000Hz : * Gain (dB) = 0dB : * : * Band Pass Filter 1 : * Frequency = 3000Hz : * Band Width = 1000Hz : * Gain = 0dB : * : * Band Pass Filter 2 : * Frequency = 6000Hz : * Band Width = 1000Hz : * Gain = 0dB : * : * Band Pass Filter 3 : * Frequency = 9000Hz : * Band Width = 1000Hz : * Gain = 0dB : * : * Band Pass Filter 4 : * Frequency = 9000Hz : * Band Width = 1000Hz : * Gain = 0dB : * : * Low Pass Filter 1 : * Band Width = 1000Hz : * Gain (dB) = 0dB : * : * AGC Threshold = -6dB : * AGC Front Boost Gain = 6dB : * AGC Post Boost Gain = 6dB : * : * Power Output = 2.5W : */ I'd appreciate if you could split this comment and interleave the parts with the verb list, so that it's easy to see what does each group of verbs do. https://review.coreboot.org/c/coreboot/+/59263/comment/1057f65e_2c976022 PS4, Line 306: Missing closing ``` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie13f62622a4cf2b14d36728a8a4a9e3ef24d6852 Gerrit-Change-Number: 59263 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 12:26:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
by Felix Held (Code Review) 15 Nov '21

15 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58253 ) Change subject: Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" ...................................................................... Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/include/bootmode.h M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/asurada/chromeos.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/brya/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/deltaur/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/eve/gpio.h M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/fizz/variants/karma/gpio.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/glados/variants/asuka/include/variant/gpio.h M src/mainboard/google/glados/variants/caroline/include/variant/gpio.h M src/mainboard/google/glados/variants/cave/include/variant/gpio.h M src/mainboard/google/glados/variants/chell/include/variant/gpio.h M src/mainboard/google/glados/variants/glados/include/variant/gpio.h M src/mainboard/google/glados/variants/lars/include/variant/gpio.h M src/mainboard/google/glados/variants/sentry/include/variant/gpio.h M src/mainboard/google/gru/chromeos.c M src/mainboard/google/guybrush/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/ambassador/gpio.c M src/mainboard/google/hatch/variants/dooly/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/duffy/gpio.c M src/mainboard/google/hatch/variants/faffy/gpio.c M src/mainboard/google/hatch/variants/genesis/gpio.c M src/mainboard/google/hatch/variants/hatch/gpio.c M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kaisa/gpio.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/moonbuggy/gpio.c M src/mainboard/google/hatch/variants/mushu/gpio.c M src/mainboard/google/hatch/variants/nightfury/gpio.c M src/mainboard/google/hatch/variants/noibat/gpio.c M src/mainboard/google/hatch/variants/palkia/gpio.c M src/mainboard/google/hatch/variants/puff/gpio.c M src/mainboard/google/hatch/variants/scout/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c M src/mainboard/google/hatch/variants/wyvern/gpio.c M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/atlas/gpio.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nautilus/gpio.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/rammus/gpio.c M src/mainboard/google/poppy/variants/soraka/gpio.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/collis/gpio.c M src/mainboard/google/volteer/variants/copano/gpio.c M src/mainboard/google/volteer/variants/halvor/gpio.c M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/todor/gpio.c M src/mainboard/google/volteer/variants/voema/gpio.c M src/mainboard/google/zork/Makefile.inc M src/mainboard/google/zork/chromeos.c M src/mainboard/google/zork/variants/baseboard/Makefile.inc D src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/intel/adlrvp/chromeos.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/kunimitsu/gpio.h M src/mainboard/intel/shadowmountain/chromeos.c M src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c M src/mainboard/intel/tglrvp/chromeos.c M src/security/vboot/bootmode.c M src/security/vboot/vboot_logic.c M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/skylake/Makefile.inc 115 files changed, 541 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/include/bootmode.h b/src/include/bootmode.h index aadecba..da2dbf6 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -11,6 +11,7 @@ int clear_recovery_mode_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); +int get_ec_is_trusted(void); /* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index cb904a0..c4770ff 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -24,3 +24,10 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 6f8f242..1aa8876 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -40,3 +40,9 @@ { return gpio_eint_poll(GPIO_H1_AP_INT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 40f98f2..9807ace 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -9,6 +9,13 @@ #include "onboard.h" +/* EC_IN_RW is GPIO 25 in samus and 14 otherwise */ +#if CONFIG(BOARD_GOOGLE_SAMUS) +#define EC_IN_RW_GPIO 25 +#else +#define EC_IN_RW_GPIO 14 +#endif + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,3 +40,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !get_gpio(EC_IN_RW_GPIO); +} diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index ce3030d..db64649 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -74,3 +74,10 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index bf7f9eb..cb636c6 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -31,3 +31,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 83b6ba0..a7d56ae 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -64,3 +64,10 @@ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 748e06e..13b673c 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -59,3 +59,9 @@ { return gpio_eint_poll(GPIO_GSC_AP_INT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index f0c1446..a11b6f9 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -64,3 +64,10 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 00fa126..c32c3b0 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -38,3 +38,9 @@ { return !gpio_get_value(GPIO_D16); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get_value(GPIO_D17); +} diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index e5ae163..ad37b20 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -32,3 +32,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 864bb29..3bee320 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -423,6 +423,9 @@ /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C14 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C20 : UART2 RX */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2 TX */ diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 7083c80..2be5295 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -98,3 +98,10 @@ if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 726736a..58ad3c3 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -97,3 +97,10 @@ pmc_soc_set_afterg3_en(true); #endif } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 7c0cc96..bc458de 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -36,3 +36,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 607486b..ad77eb5 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -225,6 +225,9 @@ /* Ensure UART pins are in native mode for H1 */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ + +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 5ee822c..d10a59f 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -36,3 +36,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index 71546aa..4787d2d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -241,6 +241,9 @@ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ + +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; const struct pad_config * __weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 2735fed..8b88f23 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -245,6 +245,9 @@ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ + +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 4e744f1..9ac4cf0 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -26,3 +26,10 @@ { return 0; } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 2987e91..5464640 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -157,3 +157,10 @@ { return !read_gpio(get_wp_status_gpio_pin()); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 1dff1ca..1adaed4 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -35,3 +35,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index 17c24a2..d21d9e7 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -219,6 +219,7 @@ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index f570006..95d2d04 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -236,6 +236,7 @@ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 45e1f67..cd71eba 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -228,6 +228,7 @@ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 1c92e51..ce78ed3 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -224,6 +224,7 @@ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index a7bcdd74..fc4eebde 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -226,6 +226,8 @@ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index acbf157..51514b2 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -215,6 +215,7 @@ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index a2052a3..b4011c7 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -223,6 +223,7 @@ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 688c0dd..479ca3d 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -49,3 +49,9 @@ return gpio_irq_status(GPIO_TPM_IRQ); } #endif + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index 3e54fa4..9875554 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/gpio.h> +#include <boardid.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> @@ -26,3 +27,14 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Board versions 1 & 2 support H1 DB, but the EC_IN_RW signal is not + routed. So emulate EC is trusted. */ + if (CONFIG(BOARD_GOOGLE_GUYBRUSH) && + (board_id() == UNDEFINED_STRAPPING_ID || board_id() < 3)) + return 1; + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 3401b82..3f585c9 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -36,3 +36,9 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index b08f062..d7fe09e 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -162,6 +162,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/hatch/variants/ambassador/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/ambassador/gpio.c +++ b/src/mainboard/google/hatch/variants/ambassador/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c index d28f1fe..37cd08c 100644 --- a/src/mainboard/google/hatch/variants/dooly/gpio.c +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -137,6 +137,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 712a918..02555a0 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -86,6 +86,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/duffy/gpio.c b/src/mainboard/google/hatch/variants/duffy/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/duffy/gpio.c +++ b/src/mainboard/google/hatch/variants/duffy/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/faffy/gpio.c b/src/mainboard/google/hatch/variants/faffy/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/faffy/gpio.c +++ b/src/mainboard/google/hatch/variants/faffy/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/hatch/variants/genesis/gpio.c index cb5c89b..66a1b8a 100644 --- a/src/mainboard/google/hatch/variants/genesis/gpio.c +++ b/src/mainboard/google/hatch/variants/genesis/gpio.c @@ -128,6 +128,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index cfd3248..dbe72dd 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -60,6 +60,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 9885802..f7c5e8f 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -124,6 +124,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index a0658b0..1020dd6 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -90,6 +90,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/kaisa/gpio.c b/src/mainboard/google/hatch/variants/kaisa/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/kaisa/gpio.c +++ b/src/mainboard/google/hatch/variants/kaisa/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index b147e41..0d55730 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -220,6 +220,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index d45e9cb..aa86932 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -106,6 +106,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c index 759768b..ba75fb7 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c +++ b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c @@ -126,6 +126,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 582d68e..4ead952 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -64,6 +64,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index 1ab10a8..a813dfa 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -120,6 +120,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/noibat/gpio.c b/src/mainboard/google/hatch/variants/noibat/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/noibat/gpio.c +++ b/src/mainboard/google/hatch/variants/noibat/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index c4d6f50..58ec12b 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -128,6 +128,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c index 5491efe..218d3db 100644 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ b/src/mainboard/google/hatch/variants/scout/gpio.c @@ -160,6 +160,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index fd8a55c..2734629 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -80,6 +80,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/wyvern/gpio.c b/src/mainboard/google/hatch/variants/wyvern/gpio.c index 5a911fc..996edc4 100644 --- a/src/mainboard/google/hatch/variants/wyvern/gpio.c +++ b/src/mainboard/google/hatch/variants/wyvern/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index a116675..9faf4ba 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -24,3 +24,9 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Stub GPIO. */ + return 0; +} diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 807e37f..239134b 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -76,3 +76,10 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 0a465c9..690a9e3 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -34,3 +34,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 3f15a3f..4c4a8be 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -37,3 +37,9 @@ { return gpio_eint_poll(CR50_IRQ); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(EC_IN_RW); +} diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index f77c822..f544167 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -8,6 +8,8 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" +#define GPIO_EC_IN_RW 21 + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,3 +41,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !get_gpio(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index c827c7d..7ffcd57 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,8 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <bootmode.h> void fill_lb_gpios(struct lb_gpios *gpios) { } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 7fe877b..9aaad2f 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -19,3 +19,9 @@ { return !gpio_get(GPIO(R1)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO(U4)); +} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 7fe877b..9aaad2f 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -19,3 +19,9 @@ { return !gpio_get(GPIO(R1)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO(U4)); +} diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 7fe877b..9aaad2f 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -19,3 +19,9 @@ { return !gpio_get(GPIO(R1)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO(U4)); +} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 9e7af27..739df2e 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -34,3 +34,9 @@ { return !gpio_get(WRITE_PROTECT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(EC_IN_RW); +} diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 9c260ab..82599ac 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -35,3 +35,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index d16c4e1..61e8e0d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -344,6 +344,8 @@ * stages. */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ + + PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ }; const struct pad_config *__weak diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 4781f7e..01a2d8e 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -64,3 +64,10 @@ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 07a13a3..e1d8fa1 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -38,3 +38,9 @@ { return !gpio_get_value(GPIO_X30); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get_value(GPIO_X23); +} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index ff39fbf..4cd9029 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -40,3 +40,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index d3ea6b5..ffea694 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -345,6 +345,9 @@ /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index d3df99e..ea9de7a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -341,6 +341,9 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 6dba783..b5ec954 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -346,6 +346,9 @@ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 37378f9..e06355a 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -331,6 +331,9 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index f534458..6324d8f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -352,6 +352,9 @@ /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 8e9e5c0..c67c560 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -349,6 +349,9 @@ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 9d52773..808ab3b 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -342,6 +342,10 @@ static const struct pad_config early_gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), + + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 773a807..d76c5e4 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -9,6 +9,9 @@ /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36 +/* The EC_IN_RW lives on SCGPIO59 */ +#define EC_IN_RW_PAD 59 + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -44,3 +47,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !score_get_gpio(EC_IN_RW_PAD); +} diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index d258678..1d1c990 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -35,3 +35,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 9bb3e45..8263459 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -368,6 +368,8 @@ /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ }; const struct pad_config * __weak diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index de54929..b60e031 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -369,6 +369,8 @@ /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 37fd817a..8337415 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -94,3 +94,10 @@ if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 0fa78c9..634e563 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -32,3 +32,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !get_gpio(14); +} diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 13a69bc..d74df82 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -19,3 +19,9 @@ { return !gpio_get(WRITE_PROTECT_L); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(EC_IN_RW); +} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 69f0fcc..4ecc228 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -128,3 +128,10 @@ { return !read_gpio(WP_SW); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 90de1e4..11b38b5 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -57,3 +57,9 @@ { return gpio_irq_status(GPIO_H1_AP_INT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index cdea2ce..9374dc4 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -56,3 +56,9 @@ { return !gpio_get(GPIO_WP); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_ECINRW); +} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index a3fe3f4..c4cd6c6 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -34,3 +34,10 @@ { return !gpio_get(GPIO_WP); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 7dcf7dc..f1eb1c3 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -43,3 +43,10 @@ { return !gpio_get(GPIO_WP); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 20469d6..9b8e2f5 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -34,3 +34,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index ac8c5c2..05c757c 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -432,6 +432,9 @@ /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), + + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), }; const struct pad_config *__weak variant_base_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/collis/gpio.c b/src/mainboard/google/volteer/variants/collis/gpio.c index 03bd91e..86919b9 100644 --- a/src/mainboard/google/volteer/variants/collis/gpio.c +++ b/src/mainboard/google/volteer/variants/collis/gpio.c @@ -204,6 +204,9 @@ /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/copano/gpio.c b/src/mainboard/google/volteer/variants/copano/gpio.c index bec58e5..933aebb 100644 --- a/src/mainboard/google/volteer/variants/copano/gpio.c +++ b/src/mainboard/google/volteer/variants/copano/gpio.c @@ -220,6 +220,9 @@ /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 7d6725a..994df04 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -233,6 +233,9 @@ /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index 69760c1..0febca8 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -221,6 +221,9 @@ /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c index 5611cca..e699027 100644 --- a/src/mainboard/google/volteer/variants/todor/gpio.c +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -231,6 +231,9 @@ /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c index 70b7f52..4f3f799 100644 --- a/src/mainboard/google/volteer/variants/voema/gpio.c +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -219,6 +219,9 @@ /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index ccc163c..a260b0f 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -10,6 +10,7 @@ ramstage-y += ec.c ramstage-y += sku_id.c +verstage-y += chromeos.c verstage-y += verstage.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index 35c002d..d649193 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -33,3 +33,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index 2764a89..437ba0b 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -1,23 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio_baseboard_common.c bootblock-y += helpers.c bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c -verstage-y += gpio_baseboard_common.c verstage-y += helpers.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c verstage-y += tpm_tis.c -romstage-y += gpio_baseboard_common.c romstage-y += helpers.c romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c romstage-y += tpm_tis.c -ramstage-y += gpio_baseboard_common.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += fsps_baseboard_trembyle.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c deleted file mode 100644 index 948ce8f..0000000 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/variants.h> -#include <soc/gpio.h> -#include <stdlib.h> -#include <variant/gpio.h> - -static const struct soc_amd_gpio early_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* PCIE_RST0_L - Fixed timings */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* FCH_ESPI_EC_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), - /* UART0_RXD - DEBUG */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - /* UART0_TXD - DEBUG */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), -}; - -const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 6f8a416..5d3e21f 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -310,3 +310,30 @@ *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } + +static const struct soc_amd_gpio early_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 62935a6..415c426 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -359,3 +359,30 @@ *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } + +static const struct soc_amd_gpio early_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index 5fe89af..fce365d 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -49,3 +49,11 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)) +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} +#endif diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index dfdb66d..7a14c86 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -39,3 +39,10 @@ { return -1; } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 902cb19..afc27cd 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -64,3 +64,10 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 09e9b7e..87a0e01 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -35,3 +35,9 @@ { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 2cd0196..439bd89 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -222,6 +222,7 @@ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index e71314f..0858754 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -34,3 +34,9 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c index 80a4264..6a74468 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c @@ -13,6 +13,8 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* A7 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* A17 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* A19 : MEM_STRAP_2 */ diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 4eeb679..dd6c666 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -47,3 +47,10 @@ gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 6c05109..3c50e4e 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -57,6 +57,16 @@ return 0; } +int __weak get_ec_is_trusted(void) +{ + /* + * If board doesn't override this, by default we always assume EC is in + * RW and untrusted. However, newer platforms are supposed to use cr50 + * BOOT_MODE to report this and won't need to override this anymore. + */ + return 0; +} + #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2973934..91d42b2 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -306,6 +306,9 @@ if (CONFIG(TPM_CR50)) check_boot_mode(ctx); + if (get_ec_is_trusted()) + ctx->flags |= VB2_CONTEXT_EC_TRUSTED; + /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(ctx); diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d857e8b..00d857c 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -44,6 +44,8 @@ ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c +verstage-y += gpio.c + smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index a557d1e..1335090 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -89,11 +89,13 @@ romstage-y += gpio_glk.c smm-y += gpio_glk.c ramstage-y += gpio_glk.c +verstage-y += gpio_glk.c else bootblock-y += gpio_apl.c romstage-y += gpio_apl.c smm-y += gpio_apl.c ramstage-y += gpio_apl.c +verstage-y += gpio_apl.c endif CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ea96caa..369f324 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += lpc.c bootblock-y += uart.c +verstage-y += gpio.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c -- To view, visit https://review.coreboot.org/c/coreboot/+/58253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Gerrit-Change-Number: 58253 Gerrit-PatchSet: 10 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59295 ) Change subject: soc/mediatek: move i2c function to common folder ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: @yu-ping and @hung-te, this patch will build fail for 8173. please review again. thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 11:41:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59295 ) Change subject: soc/mediatek: move i2c function to common folder ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/i2c.c: https://review.coreboot.org/c/coreboot/+/59295/comment/8ca6ce93_babbe220 PS4, Line 36: __weak void mtk_i2c_config_timing(struct mt_i2c_regs *regs, > open brace '{' following function definitions go on the next line Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 11:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59295 to look at the new patch set (#5). Change subject: soc/mediatek: move i2c function to common folder ...................................................................... soc/mediatek: move i2c function to common folder Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/i2c.h M src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/i2c.h M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/include/soc/i2c.h 10 files changed, 295 insertions(+), 257 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59295/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by build bot (Jenkins) (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59295 ) Change subject: soc/mediatek: move i2c function to common folder ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/i2c.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133240): https://review.coreboot.org/c/coreboot/+/59295/comment/3d9cd822_26767a7c PS4, Line 36: __weak void mtk_i2c_config_timing(struct mt_i2c_regs *regs, open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 15 Nov 2021 11:25:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add I2C driver support
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59296 to look at the new patch set (#4). Change subject: soc/mediatek/mt8186: Add I2C driver support ...................................................................... soc/mediatek/mt8186: Add I2C driver support Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang <housong.zhang(a)mediatek.corp-partner.google.com> Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/i2c.c A src/soc/mediatek/mt8186/include/soc/i2c.h 3 files changed, 217 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59296/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Gerrit-Change-Number: 59296 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Rex-BC Chen (Code Review) 15 Nov '21

15 Nov '21

Attention is currently required from: Hung-Te Lin, Xi Chen, Rex-BC Chen. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59295 to look at the new patch set (#4). Change subject: soc/mediatek: move i2c function to common folder ...................................................................... soc/mediatek: move i2c function to common folder Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/i2c.h M src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/i2c.h M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/include/soc/i2c.h 10 files changed, 293 insertions(+), 257 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59295/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree
by Felix Held (Code Review) 15 Nov '21

15 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59259 ) Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree ...................................................................... mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree With latest hardware revision all clock outputs will be used on this mainboard. For this reason set all clock source mappings to 'PCIE_CLK_FREE' to have a free running clock. Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 39789be..ca90557 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -55,9 +55,9 @@ register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" -- To view, visit https://review.coreboot.org/c/coreboot/+/59259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae Gerrit-Change-Number: 59259 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2021