coreboot-gerrit November 2021

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Change in coreboot[master]: lib: Add a mutex
by Julius Werner (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 2: (2 comments) File src/include/mutex.h: PS2: License File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/1e15547e_837c1e96 PS2, Line 24: #if ENV_X86 I'm honestly not sure if combining this stuff like this is a good idea, because as you can see here you're forced to get into architectural details pretty quickly. On arm64, the equivalent to the PAUSE instruction would be a WFE instruction here and then a SEV instruction in unlock(). So you need to have different architectural hooks in different places for each architecture to the point where in the end it would probably become easier to just implement the whole thing separately for each. I'm also not exactly sure how GCC translates the generic atomics into instructions on Arm, and the load-acquire/store-release rules there can get very tricky and have weird requirements to make them work. Usually, each architecture already brings its assembly reference code for these kinds of things anyway, and it's easier to just copy that in (and throw in a call to thread_yield() somewhere) than trying to do it all yourself, especially in generic C. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:42:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56322 ) Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: PTAL, I fixed the merge conflict by rebasing. -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:37:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Rob Barnes, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56322 to look at the new patch set (#7). Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware The SPI DMA controller was not completely functional prior to RN/CZN. This code can be used to sanity check the DMA hardware. BUG=b:179699789 TEST=Boot guybrush with VERIFY=1 and make sure no DMA errors occur. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 --- M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/spi_dma.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56322/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/hyperthreading: Add missing header <arch/cpu.h>
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Patrick Rudolph. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59356 ) Change subject: cpu/intel/hyperthreading: Add missing header <arch/cpu.h> ...................................................................... cpu/intel/hyperthreading: Add missing header <arch/cpu.h> This file is using cpuid_result and cpuid(). I also removed the spinlock header since it's not used. This is what was previously providing the cpu.h header. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idc3daa64562c4a4d57b678f13726509b480ba050 --- M src/cpu/intel/hyperthreading/intel_sibling.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/59356/1 diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 93d29d4..9fde031 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/hyperthreading.h> #include <device/device.h> #include <option.h> -#include <smp/spinlock.h> /* Intel hyper-threading requires serialized CPU init. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc3daa64562c4a4d57b678f13726509b480ba050 Gerrit-Change-Number: 59356 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Remove spinlock dependency on threading
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Paul Menzel, Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59322 ) Change subject: arch/x86: Remove spinlock dependency on threading ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59322/comment/63628f75_fd454d36 PS4, Line 7: arch/x86: Remove spinlock dependency on threading. > Please remove the dot/period at the end of the commit message summary. Done https://review.coreboot.org/c/coreboot/+/59322/comment/66837a31_e2902af8 PS4, Line 12: This is mostly a revert of CB:56320. > Please also mention the commit hash and summary, as that (hash) is what git works with. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d0cd2bcd82721098ca24ae2368bb6a16a07df4 Gerrit-Change-Number: 59322 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:33:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Remove spinlock dependency on threading
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Paul Menzel, Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Hello Paul Menzel, Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59322 to look at the new patch set (#5). Change subject: arch/x86: Remove spinlock dependency on threading ...................................................................... arch/x86: Remove spinlock dependency on threading Since we only have one spinlock caller left, we can move the thread_coop_ calls out of the spinlock. This is mostly a revert of commit a98d302fe9dc ("x86/smp/spinlock: Disable thread coop when taking spinlock") BUG=b:179699789 TEST=Boot guybrush to OS with threading enabled Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I55d0cd2bcd82721098ca24ae2368bb6a16a07df4 --- M src/arch/x86/include/arch/smp/spinlock.h M src/console/printk.c 2 files changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/59322/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55d0cd2bcd82721098ca24ae2368bb6a16a07df4 Gerrit-Change-Number: 59322 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56580 ) Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... Patch Set 13: (1 comment) File src/commonlib/mem_pool.c: https://review.coreboot.org/c/coreboot/+/56580/comment/5eed14c5_d328b447 PS13, Line 11: return NULL; > nit: not sure why this is still here when you assert that alignment can't be 0? Only mem_pool_init asserts. Using MEM_POOL_INIT it's still possible (and desirable) to set a 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 13 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:30:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58962 ) Change subject: lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload ...................................................................... lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preload Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/include/symbols.h M src/lib/Kconfig M src/lib/prog_loaders.c M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/cpu/Kconfig M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 6 files changed, 9 insertions(+), 77 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/include/symbols.h b/src/include/symbols.h index 52624d4..3e4694b 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -52,7 +52,6 @@ /* Regions for execution units. */ -DECLARE_REGION(payload_preload_cache) DECLARE_REGION(payload) /* "program" always refers to the current execution unit. */ DECLARE_REGION(program) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 0f18425..0142300 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -114,14 +114,3 @@ in the background before they are actually required. This feature depends on the read-only boot_device having a DMA controller to perform the background transfer. - -config PAYLOAD_PRELOAD - bool - depends on COOP_MULTITASKING - help - On some systems with SPI DMA controllers, it is possible to preload - the payload while ramstage is executing. This can be selected by the - SoC to enable payload preloading. - - The SoC needs to define a payload_preload_cache region where the - raw payload can be placed. diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 1a361ea..8ad646a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -127,71 +127,37 @@ static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); -static struct thread_handle payload_preload_handle; - -static enum cb_err payload_preload_thread_entry(void *arg) -{ - size_t size; - struct prog *payload = &global_payload; - - printk(BIOS_DEBUG, "Preloading payload\n"); - - payload->cbfs_type = CBFS_TYPE_QUERY; - - size = cbfs_type_load(prog_name(payload), _payload_preload_cache, - REGION_SIZE(payload_preload_cache), &payload->cbfs_type); - - if (!size) { - printk(BIOS_ERR, "ERROR: Preloading payload failed\n"); - return CB_ERR; - } - - printk(BIOS_DEBUG, "Preloading payload complete\n"); - - return CB_SUCCESS; -} - void payload_preload(void) { - struct thread_handle *handle = &payload_preload_handle; - - if (!CONFIG(PAYLOAD_PRELOAD)) + if (!CONFIG(CBFS_PRELOAD)) return; - if (thread_run(handle, payload_preload_thread_entry, NULL)) - printk(BIOS_ERR, "ERROR: Failed to start payload preload thread\n"); + cbfs_preload(global_payload.name); } void payload_load(void) { struct prog *payload = &global_payload; - struct thread_handle *handle = &payload_preload_handle; - void *mapping = NULL; - void *buffer; + void *mapping; timestamp_add_now(TS_LOAD_PAYLOAD); if (prog_locate_hook(payload)) goto out; - if (CONFIG(PAYLOAD_PRELOAD) && thread_join(handle) == CB_SUCCESS) { - buffer = _payload_preload_cache; - } else { - payload->cbfs_type = CBFS_TYPE_QUERY; - mapping = cbfs_type_map(prog_name(payload), NULL, &payload->cbfs_type); - buffer = mapping; - } + payload->cbfs_type = CBFS_TYPE_QUERY; + mapping = cbfs_type_map(prog_name(payload), NULL, &payload->cbfs_type); - if (!buffer) + if (!mapping) goto out; switch (prog_cbfs_type(payload)) { case CBFS_TYPE_SELF: /* Simple ELF */ - selfload_mapped(payload, buffer, BM_MEM_RAM); + selfload_mapped(payload, mapping, BM_MEM_RAM); break; case CBFS_TYPE_FIT: /* Flattened image tree */ if (CONFIG(PAYLOAD_FIT_SUPPORT)) { - fit_payload(payload, buffer); + fit_payload(payload, mapping); break; } /* else fall-through */ default: @@ -200,8 +166,7 @@ break; } - if (mapping) - cbfs_unmap(mapping); + cbfs_unmap(mapping); out: if (prog_entry(payload) == NULL) die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n"); diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 3fb5085..6c8c3e5 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -197,7 +197,6 @@ select COOP_MULTITASKING select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select CBFS_PRELOAD - select PAYLOAD_PRELOAD help When enabled, the platform will use the LPC SPI DMA controller to asynchronously load contents from the SPI ROM. This will improve diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 3dd1e33..7f50965 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -29,16 +29,6 @@ help The size of the cbfs_cache region. -config PAYLOAD_PRELOAD_CACHE_SIZE - hex - default 0x30000 - depends on PAYLOAD_PRELOAD - help - This config sets the size of the payload_preload_cache memory region. - It is used as the destination for the raw payload. This space is only - populated during non-S3, so it doesn't need to be reserved in the - EARLY_RESERVED_DRAM region. - endif # SOC_AMD_COMMON_BLOCK_NONCAR config SOC_AMD_COMMON_BLOCK_MCA_COMMON diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index a542b7d..e42174f 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -106,16 +106,6 @@ EARLY_RESERVED_DRAM_END(.) -#if CONFIG(PAYLOAD_PRELOAD) - /* - * This section is outside the early_reserved_dram section. We only read - * the payload on non-S3 boots, so we don't need to reserve it from the - * OS. The 64 byte alignment is required by the SPI DMA controller. - */ - . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); - REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE) -#endif - RAMSTAGE(CONFIG_RAMBASE, 8M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/58962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Gerrit-Change-Number: 58962 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Rob Barnes, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56322 ) Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56322/comment/996e534f_45efb729 PS6, Line 10: This code can be used to sanity check the DMA hardware. > Please mention, that it’s a new Kconfig option next time. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:20:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Use default kernel secdata size
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Andrey Pronin, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58669 ) Change subject: security/vboot: Use default kernel secdata size ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed Gerrit-Change-Number: 58669 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:08:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021