coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Angel Pons (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59310/comment/0aabf80e_3a5f71ea PS3, Line 67: ~ > Ack Yes, the clear-set approach avoids having to use bitwise negations, which can result in compiler warnings with 16-bit and 8-bit operations because of integer promotion rules -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 20:08:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59310/comment/1163dabe_9de45537 PS3, Line 67: ~ > ahh, make sense :) Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 20:01:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59310/comment/5511e9fc_963db7f0 PS3, Line 67: ~ > the `~` is already in the `clrsetbits32` macro, so I think you do not actually want the tilde here, […] ahh, make sense :) -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 20:01:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shu...
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59270 ) Change subject: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shutdown ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59270/comment/71923501_bc37db0f PS4, Line 95: .pch_thermal_trip = 100, > Isn't there usually a recommended value per-chipset? Yes, you are right. this should be optimal value based on thermal team. > Just wondering if `chipset.cb` for alderlake makes more sense here for setting the value to 100? Yes, i believe that makes more sense. The reason I have moved to all mainboard to allow any override if required but don't think that might even required. Will move default 100 degree to chipset.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/59270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79 Gerrit-Change-Number: 59270 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 19:59:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59310/comment/8c0678e8_10d58cf4 PS3, Line 67: ~ the `~` is already in the `clrsetbits32` macro, so I think you do not actually want the tilde here, i.e. you pass in the mask of the bits you want to have cleared, and the macro does the bit-inversion -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 19:58:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shu...
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59270 ) Change subject: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shutdown ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59270/comment/65b046e2_8163f2ad PS4, Line 95: .pch_thermal_trip = 100, Isn't there usually a recommended value per-chipset? Just wondering if `chipset.cb` for alderlake makes more sense here for setting the value to 100? -- To view, visit https://review.coreboot.org/c/coreboot/+/59270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79 Gerrit-Change-Number: 59270 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 19:54:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 2: (1 comment) File src/lib/mutex.c: https://review.coreboot.org/c/coreboot/+/59320/comment/7bbd1e40_767985bb PS2, Line 24: #if ENV_X86 > I'm honestly not sure if combining this stuff like this is a good idea, because as you can see here […] I haven't specifically looked at the ARM assembly generated by this. ENV_STAGE_SUPPORTS_SMP always evaluates to false for ARM platforms so we will never use this code path. But from my reading (https://gcc.gnu.org/wiki/Atomic/GCCMM/AtomicSync) is meant to handle all the correct barriers as long as you specify the correct memory order. As for the WFE and SEV. I say we cross the bridge when we get there. We can make arch specific `sleep/pasue` and `wake/resume` methods if we need them. I wanted to keep it simple since this is only targeting RISCV and x86 right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 19:03:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Julius Werner (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Raul Rangel, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 2: (1 comment) File src/include/mutex.h: https://review.coreboot.org/c/coreboot/+/59320/comment/1c8343a6_ffaee121 PS2, Line 11: void mutex_unlock(struct mutex *mutex); These should be static inline no-ops when neither SMP nor threading is enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:55:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Felix Held (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS7: > i'll re-test this one re-teste and it gets to the payload. output from bootblock: coreboot-4.14-2762-g11e7308c13 Tue Nov 16 17:28:33 UTC 2021 bootblock starting (log level: 7)... Family_Model: 00670f00 Set power off after power failure. PMxC0 STATUS: 0x80800 DoReset BIT11 SPI normal read speed: 16.66 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) I2C bus 1 version 0x3132312a DW I2C bus 1 at 0xfedc3000 (400 KHz) FMAP: Found "FLASH" version 1.1 at 0x10000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 4 FMAP: area COREBOOT found @ 10200 (16711168 bytes) CBFS: mcache @0x00035800 built for 15 files, used 0x328 of 0x4000 bytes CBFS: Found 'fallback/romstage' @0x80 size 0xa690 in mcache @0x0003582c BS: bootblock times (exec / console): total (unknown) / 64 ms the show_spi_speeds_and_modes call in stoneyridge runs before the mainboard's bootblock_mainboard_init function configures the SPI interface, so this is exactly what i'd expect here. This change should also speed up the boot process on the stoneyridge chromebooks a bit, since it likely increases the spi speed when the psp gets it firmware components before coreboot starts -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:47:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/mem_pool: Allow configuring the alignment
by Julius Werner (Code Review) 16 Nov '21

16 Nov '21

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56580 ) Change subject: commonlib/mem_pool: Allow configuring the alignment ...................................................................... Patch Set 13: (1 comment) File src/commonlib/mem_pool.c: https://review.coreboot.org/c/coreboot/+/56580/comment/07e2a106_46131c26 PS13, Line 11: return NULL; > Only mem_pool_init asserts. Using MEM_POOL_INIT it's still possible (and desirable) to set a 0. Only when size is 0 too though, right? So then it would drop out in line 18 anyway. (In fact, would probably not hurt to have a _Static_assert(!size == !alignment) in MEM_POOL_INIT().) -- To view, visit https://review.coreboot.org/c/coreboot/+/56580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075 Gerrit-Change-Number: 56580 Gerrit-PatchSet: 13 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 18:47:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021