coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Add Acoustic noise mitigation UPDs
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Chen Wisley, Wisley Chen, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58944 ) Change subject: soc/intel/alderlake: Add Acoustic noise mitigation UPDs ...................................................................... Patch Set 4: (3 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/58944/comment/7e12ec00_3ec173b3 PS4, Line 546: * : * Enable or Disable Acoustic Noise Mitigation feature : */ nit: single-line comment will work here https://review.coreboot.org/c/coreboot/+/58944/comment/95b9e697_1f85d08b PS4, Line 550: /* : * Disable Fast Slew Rate for Deep Package C States for VR domains : */ nit: single-line comment will work here File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/58944/comment/50be5d3e_f4c7743b PS4, Line 746: for (int i = 0; i < NUM_VR_DOMAINS; i++) { : s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; : s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i]; : } This should probably be guarded by `if (s_cfg->AcousticNoiseMitigation) {` -- To view, visit https://review.coreboot.org/c/coreboot/+/58944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Gerrit-Change-Number: 58944 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:40:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7280: gpio: Support eGPIO scheme
by Shelley Chen (Code Review) 16 Nov '21

16 Nov '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58580 ) Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme ...................................................................... qualcomm/sc7280: gpio: Support eGPIO scheme eGPIO is a scheme which allows special power island domain IOs to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. Allow the eGPIO to be configured via gpio_configure API to be used as a TLMM gpio. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58580 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/gpio.c M src/soc/qualcomm/common/include/soc/gpio_common.h 2 files changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/common/gpio.c b/src/soc/qualcomm/common/gpio.c index 1ed8e8a..5053f3b 100644 --- a/src/soc/qualcomm/common/gpio.c +++ b/src/soc/qualcomm/common/gpio.c @@ -16,7 +16,9 @@ reg_val = ((enable & GPIO_BMSK) << GPIO_CFG_OE_SHFT) | ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | - ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT) | + ((read32(&regs->cfg) & GPIO_CFG_EGPIO_BMSK) + << GPIO_CFG_EGPIO_SHFT); write32(&regs->cfg, reg_val); } diff --git a/src/soc/qualcomm/common/include/soc/gpio_common.h b/src/soc/qualcomm/common/include/soc/gpio_common.h index 20f947a..18cd040 100644 --- a/src/soc/qualcomm/common/include/soc/gpio_common.h +++ b/src/soc/qualcomm/common/include/soc/gpio_common.h @@ -21,6 +21,7 @@ GPIO_CFG_PULL_BMSK = 0x3, GPIO_CFG_FUNC_BMSK = 0xF, GPIO_CFG_DRV_BMSK = 0x7, + GPIO_CFG_EGPIO_BMSK = 0x800, }; /* GPIO TLMM INTR: Shift */ @@ -35,6 +36,7 @@ GPIO_CFG_FUNC_SHFT = 2, GPIO_CFG_DRV_SHFT = 6, GPIO_CFG_OE_SHFT = 9, + GPIO_CFG_EGPIO_SHFT = 1, }; /* GPIO IO: Shift */ -- To view, visit https://review.coreboot.org/c/coreboot/+/58580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 Gerrit-Change-Number: 58580 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: qualcomm/sc7280: gpio: Support eGPIO scheme
by Shelley Chen (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Ravi kumar, Taniya Das, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58580 ) Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme ...................................................................... Patch Set 7: (3 comments) File src/soc/qualcomm/common/gpio.c: https://review.coreboot.org/c/coreboot/+/58580/comment/21c808b7_b24e5407 PS2, Line 21: if ((read32(&regs->cfg) >> GPIO_EGPIO_SHFT) & GPIO_EGPIO_BMSK) > Would this work? […] Done File src/soc/qualcomm/common/include/soc/gpio_common.h: https://review.coreboot.org/c/coreboot/+/58580/comment/271b1ece_9d3ba528 PS6, Line 24: BIT(11) > Let's do 0x800 since everything else is in hex. Done File src/soc/qualcomm/common/include/soc/gpio_common.h: https://review.coreboot.org/c/coreboot/+/58580/comment/97d6772e_79589e2d PS2, Line 87: enum egpio_cfg { > Yes, we might need to add more fields in future, thus added the enum. This has been removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/58580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 Gerrit-Change-Number: 58580 Gerrit-PatchSet: 7 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:26:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7280: gpio: Support eGPIO scheme
by Shelley Chen (Code Review) 16 Nov '21

16 Nov '21

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Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58896 ) Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... Patch Set 7: (1 comment) Patchset: PS2: > My plan about these "mode switches" and their weak alternatives: […] That's an interesting thought, I would love more compile-time or even loud run-time errors over silent ones. -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:17:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu,soc/amd/common/block/cpu: Add preload_microcode
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58963 ) Change subject: src/cpu,soc/amd/common/block/cpu: Add preload_microcode ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/58963/comment/c5ef303e_e3d91a7a PS2, Line 127: preload_microcode > Where is it getting called? I haven't pushed a CL to call this yet. Waiting for all the other dependencies to land so i can time and order everything correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/58963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Gerrit-Change-Number: 58963 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:16:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59348 ) Change subject: mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If084a8af941b36a8f3f608271078e32b093d9108 Gerrit-Change-Number: 59348 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:15:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib/hardwaremain: Run timers more frequently
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58955 ) Change subject: lib/hardwaremain: Run timers more frequently ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58955/comment/686c45ac_8d80ecb8 PS2, Line 14: see SPI transactions progress faster > Why are they faster now? How much faster is the boot? Because we poll the SPI DMA controller more often to see if it's completed the transaction. This allows us to trigger another transaction. It doesn't currently change boot time, the SPI transaction just gets marked as complete sooner. -- To view, visit https://review.coreboot.org/c/coreboot/+/58955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8 Gerrit-Change-Number: 58955 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up common code for thermal configuration
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59271 ) Change subject: soc/intel/alderlake: Hook up common code for thermal configuration ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59271/comment/9395e5de_9549cb23 PS3, Line 7: Allow thermal configuration > How about this: […] Ack https://review.coreboot.org/c/coreboot/+/59271/comment/6e544da0_7faa0cab PS3, Line 7: for ADL > Not needed. Already mentioned in the first part. Ack Patchset: PS3: > Do we need this as early as possible? Like rom-stage before MRC training to prevent some HW issue? We might need do this prior to FSP-S otherwise FSP-S will perform those thermal register lockdown and it would result RO while coreeboot attempts to perform thermal configuration. Hence, coreboot decides to perform thermal configuration prior FSP-S starts its execution and disallow FSP to override those settings. You can find some details in commit msg as well Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:11:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/02ef3e5c_d4b9e1f9 PS8, Line 57: static void thermal_or32(uintptr_t addr, uint32_t ordata) : { : uint32_t data32; : : data32 = read32p(addr); : data32 |= ordata; : write32p(addr, data32); : } > `setbits32` ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:11:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021