coreboot-gerrit November 2021

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59310/comment/17521f92_42170169 PS2, Line 77: thermal_rmw32 > Why not just use `clrsetbits32` ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:11:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Hook up common code for thermal configuration
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59271 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Hook up common code for thermal configuration ...................................................................... soc/intel/alderlake: Hook up common code for thermal configuration Thermal configuration registers are now located behind PMC PWRMBASE for Alder Lake Point PCH. Hence, ADL SoC to select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold is being set as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. BUG=b:193774296 TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59271/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59209 to look at the new patch set (#9). Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... soc/intel/../thermal: Add support for thermal config behind PMC device Thermal configuration has evolved over PCH generations where latest PCH has provided an option to allow thermal configuration using PMC PWRMBASE registers. This patch adds an option for impacted SoC to select the Kconfig for allowing thermal configuration using PMC PCH MMIO space. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp platform. Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/thermal.h M src/soc/intel/common/block/thermal/Kconfig M src/soc/intel/common/block/thermal/thermal.c 3 files changed, 113 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59209/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Subrata Banik (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59310 to look at the new patch set (#3). Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... soc/intel/../thermal: Use `clrsetbits32` API for setting LTT This patch uses `clrsetbits32` helper function to set thermal device Low Temp Threshold (LTT) value. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp with this change. Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/59310/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Sean Rhodes (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph, Tim Crawford, SRIDHAR SIRICILLA, Tim Wawrzynczak, Evgeny Zinoviev, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 91: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/b481f644_8d51b981 PS90, Line 991: /* (CS)ME Disable Command */ : struct me_disable_command { : struct mkhi_hdr hdr; : uint32_t rule_id; : uint8_t rule_len; : uint32_t rule_data; : } __packed me_disable = { : .hdr = { : .group_id = MKHI_GROUP_ID_FWCAPS, : .command = MKHI_SET_ME_DISABLE, : }, : .rule_id = ME_DISABLE_RULE_ID, : .rule_len = ME_DISABLE_RULE_LENGTH, : .rule_data = ME_DISABLE_COMMAND, : }; : : struct me_disable_reply { : struct mkhi_hdr hdr; : uint32_t rule_id; : } __packed; : : struct me_disable_reply disable_reply; : : size_t disable_reply_size; : : /* (CS)ME Enable Command */ : struct me_enable_command { : struct mkhi_hdr hdr; : } me_enable = { : .hdr = { : .group_id = MKHI_GROUP_ID_BUP_COMMON, : .command = MKHI_SET_ME_ENABLE, : }, : }; : : struct me_enable_reply { : struct mkhi_hdr hdr; : } __packed; : : struct me_enable_reply enable_reply; : : size_t enable_reply_size; > Is there a reason these are global-scoped and not at least file-scoped or function-scoped? I don't t […] Is that okay? -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 91 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:09:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Correct touchpad GPE settings
by YH Lin (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59345 ) Change subject: mb/google/brya/var/taeko: Correct touchpad GPE settings ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24 Gerrit-Change-Number: 59345 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:07:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: disabled autonomous GPIO power management
by YH Lin (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Joey Peng, Tim Wawrzynczak. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59325 ) Change subject: mb/google/brya/var/taeko: disabled autonomous GPIO power management ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Gerrit-Change-Number: 59325 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:07:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58132 ) Change subject: soc/intel/alderlake: Add the CnviDdrRfimDisable configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/58132/comment/5237b0e2_ee78898d PS6, Line 532: /* CNVi DDR RFIM Enable/Disable : * Default 0. Setting this to 1 disables CNVi DDR RFIM. : */ : bool CnviDdrRfimDisable; > Right now it is by default enable from FSP. […] Sorry if I'm not clear, in the devicetree, fields that are not explicitly set, will default to 0. We would rather have the default for this UPD be 0 (not necessarily all ADL boards will have CNVI or want to use RFIM), so this should be opt-in on the devicetree option. -- To view, visit https://review.coreboot.org/c/coreboot/+/58132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518 Gerrit-Change-Number: 58132 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 17:06:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Patrick Rudolph, Tim Crawford, Sean Rhodes, SRIDHAR SIRICILLA, Evgeny Zinoviev, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 90: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/4017c34d_294defbd PS90, Line 991: /* (CS)ME Disable Command */ : struct me_disable_command { : struct mkhi_hdr hdr; : uint32_t rule_id; : uint8_t rule_len; : uint32_t rule_data; : } __packed me_disable = { : .hdr = { : .group_id = MKHI_GROUP_ID_FWCAPS, : .command = MKHI_SET_ME_DISABLE, : }, : .rule_id = ME_DISABLE_RULE_ID, : .rule_len = ME_DISABLE_RULE_LENGTH, : .rule_data = ME_DISABLE_COMMAND, : }; : : struct me_disable_reply { : struct mkhi_hdr hdr; : uint32_t rule_id; : } __packed; : : struct me_disable_reply disable_reply; : : size_t disable_reply_size; : : /* (CS)ME Enable Command */ : struct me_enable_command { : struct mkhi_hdr hdr; : } me_enable = { : .hdr = { : .group_id = MKHI_GROUP_ID_BUP_COMMON, : .command = MKHI_SET_ME_ENABLE, : }, : }; : : struct me_enable_reply { : struct mkhi_hdr hdr; : } __packed; : : struct me_enable_reply enable_reply; : : size_t enable_reply_size; Is there a reason these are global-scoped and not at least file-scoped or function-scoped? I don't think I see the values being used across function calls? -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 90 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Nov 2021 16:59:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cyan: use shared touchpad/touchscreen interrupts
by Matt DeVillier (Code Review) 16 Nov '21

16 Nov '21

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59336 ) Change subject: mb/google/cyan: use shared touchpad/touchscreen interrupts ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > does Linux care about exclusive vs. […] not that I've seen, since the drivers seem to fail more gracefully if probing the device fails -- To view, visit https://review.coreboot.org/c/coreboot/+/59336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0 Gerrit-Change-Number: 59336 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 16:53:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021