coreboot-gerrit November 2021

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Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by Kyösti Mälkki (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Julius Werner. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58896 ) Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... Patch Set 7: (1 comment) File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/58896/comment/0e56cfd6_9bd710c3 PS7, Line 67: } > Does anyone know what this is even good for? As far as I can tell this always gets overwritten by de […] I don't know, can you answer on include/bootmode.h comment about using get_is_trusted() here instead. CB:58253 was unknown to me until it was merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 22:57:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: device.h: Remove unused entries in struct bus
by Paul Menzel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59364 ) Change subject: device.h: Remove unused entries in struct bus ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ddb1779180a06d1feabf8bf13a44765c2f5efe9 Gerrit-Change-Number: 59364 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 16 Nov 2021 22:40:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core
by Paul Menzel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Michael Niewöhner, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 1: (12 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59359/comment/980a4ae1_5ecc9c74 PS1, Line 7: Implements Implement https://review.coreboot.org/c/coreboot/+/59359/comment/fea2db51_a5ee26f7 PS1, Line 11: update updates https://review.coreboot.org/c/coreboot/+/59359/comment/22699d51_35223721 PS1, Line 18: generate generates https://review.coreboot.org/c/coreboot/+/59359/comment/e9999726_b03246e6 PS1, Line 20: update updates https://review.coreboot.org/c/coreboot/+/59359/comment/3b087219_5b2fe875 PS1, Line 24: Cpu CPU https://review.coreboot.org/c/coreboot/+/59359/comment/10eb8ba7_52e41ea8 PS1, Line 25: Nominal frequency or performance https://review.coreboot.org/c/coreboot/+/59359/comment/2183ed62_bb5e5fe0 PS1, Line 25: cpu CPU https://review.coreboot.org/c/coreboot/+/59359/comment/4c0a8d42_1ac7a620 PS1, Line 27: It also updates GNVS structure. It also adds the new members to the GNVS structure, as those are consumed(?) …. https://review.coreboot.org/c/coreboot/+/59359/comment/e387c4c5_e18dc63c PS1, Line 29: TEST=Verified on Brya How? https://review.coreboot.org/c/coreboot/+/59359/comment/37736b27_2dbe2d9f PS1, Line 34: methods to generate ACPI code. ???? https://review.coreboot.org/c/coreboot/+/59359/comment/fd94b906_4716480a PS1, Line 36: Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca One Change-Id should be enough. File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/59359/comment/2ca5fdb2_10a2a7cb PS1, Line 376: int unsigned int? But the signature of `cpu_init_cppc_config()` seems to use `uint32_t`. -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 22:40:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Call the set_efs_table for Stoneyridge
by Paul Menzel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58871 ) Change subject: amdfwtool: Call the set_efs_table for Stoneyridge ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58871/comment/26c0446c_fd804483 PS7, Line 8: Please describe the problem/motivataion. https://review.coreboot.org/c/coreboot/+/58871/comment/56720402_d39b62a2 PS7, Line 9: Related to https://review.coreboot.org/c/coreboot/+/58555 Please also add the git commit (short) hash and summary. -- To view, visit https://review.coreboot.org/c/coreboot/+/58871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Gerrit-Change-Number: 58871 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 22:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Add support for creating IFWI
by Sean Rhodes (Code Review) 16 Nov '21

16 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59366 ) Change subject: soc/intel/apollolake: Add support for creating IFWI ...................................................................... soc/intel/apollolake: Add support for creating IFWI Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I840ae803fe9fc83a0d1aeb48adf757e096ac5639 --- M Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc A src/soc/intel/apollolake/stitch/OEMKeyManifest.xml A src/soc/intel/apollolake/stitch/bios.xml A src/soc/intel/apollolake/stitch/meu_config.xml.in A src/soc/intel/apollolake/stitch/spi.xml.in 7 files changed, 852 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/59366/1 diff --git a/Makefile.inc b/Makefile.inc index b784f3e..59c1510 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1285,3 +1285,82 @@ done endif + +# IFWI Stitching + +ifeq ($(CONFIG_IFWI_STITCH),y) + +coreboot: $(obj)/coreboot-ifwi.rom + +$(objcbfs)/ibbl.rom: $(CBFSTOOL) $(objcbfs)/bootblock.bin + cp $(objcbfs)/bootblock.bin $@ + +$(objcbfs)/ibbm.rom: + truncate -s 4096 $@ + +$(objcbfs)/obb.rom: $(CBFSTOOL) $(obj)/coreboot.rom + $(CBFSTOOL) $(obj)/coreboot.rom read -r IFWI -f $@ + +# 1. Create a hash of the private key +$(obj)/private_hash: $(obj)/meu $(obj)/meu_config.xml $(obj)/private.pem + $(obj)/meu -cfg $(obj)/meu_config.xml -keyhash $@ -key $(obj)/private.pem + +# 2. Configure meu_config.xml +$(obj)/meu_config.xml: + sed \ + -e 's%@signing_key@%$(obj)/private.pem%g' \ + src/soc/intel/apollolake/stitch/meu_config.xml.in > $@ + +# 2. Configure spi.xml +hash=$(shell cat $(obj)/private_hash.txt) + +ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) +patch1=3rdparty/intel-microcode/intel-ucode/06-7a-01 +patch2=3rdparty/intel-microcode/intel-uco$(obj)/ISH.bin de/06-7a-08 +sku=GLK +region=4158 +else +patch1=3rdparty/intel-microcode/intel-ucode/06-5c-09 +patch2=3rdparty/intel-microcode/intel-ucode/06-5c-0a +sku=APL +region=415 +bom3="$SourceDir/build/INTC_pdt_APL_NS_BOM3_SENSORS" +endif + +ifeq ($(CONFIG_IFWI_BOOTGUARD),y) +bootguard=Boot Guard Profile 2 - VM +else +bootguard=Boot Guard Profile 0 - Legacy +endif + +$(obj)/spi.xml: $(obj)/private_hash + sed \ + -e 's%@signing_key@%$(obj)/private.pem%g' \ + -e 's%@key_hash@%$(hash)%g' \ + -e 's%@patch1@%$(patch1)%g' \ + -e 's%@patch2@%$(patch2)%g' \ + -e "s%@sku@%$(sku)%g" \ + -e 's%@region@%$(region)%g' \ + -e 's%@bootguard@%$(bootguard)%g' \ + -e 's%@bom3@%$(bom3)%g' \ + src/soc/intel/apollolake/stitch/spi.xml.in > $@ + +# 4. Create bios.bin +$(obj)/bios.bin: $(objcbfs)/ibbl.rom $(objcbfs)/ibbm.rom $(objcbfs)/obb.rom $(obj)/meu $(obj)/meu_config.xml + $(obj)/meu -f src/soc/intel/apollolake/stitch/bios.xml -cfg $(obj)/meu_config.xml -o $@ -key $(CONFIG_IFWI_PRIVATE_KEY) + +# 5. Create oemkeymn2.bin +$(obj)/oemkeymn2.bin: $(obj)/meu $(obj)/private_hash + $(obj)/meu -f src/soc/intel/apollolake/stitch/OEMKeyManifest.xml -cfg $(obj)/meu_config.xml -o $@ + +# 7. Create coreboot.rom +$(obj)/coreboot-ifwi.rom: $(obj)/cse_image.bin $(obj)/bios.bin \ + $(obj)/pmcp.bin $(obj)/smip_iafw.bin \ + $(obj)/pdt.bin \ + $(obj)/fit $(obj)/vsccommn.bin \ + $(obj)/meu $(obj)/spi.xml \ + $(obj)/oemkeymn2.bin + $(obj)/fit -b -f $(obj)/spi.xml -o $@ -st_path /usr/bin/openssl + +endif + diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 45e21dd..e200342 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -20,6 +20,75 @@ if SOC_INTEL_APOLLOLAKE +config IFWI_STITCH + bool "Stitch with FIT" + default n + help + Stitch IFWI image using Intels FIT and MEU tools + +if IFWI_STITCH + +# Blobs +config IFWI_CSE_IMAGE + string "cse_image.bin is required" + default "../stitch/cse_image.bin" + +config IFWI_PMCP + string "pmcp.bin is required" + default "../stitch/pmcp.bin" + +config IFWI_DSP_FW + string "dsp_fw.bin is optional" + help + "../stitch/dsp_fw.bin" + +config IFWI_IUNIT + string "iUnit.bin is optional" + help + "../stitch/iUnit.bin" + +config IFWI_ISH_FW + string "ish.bin is optional" + help + "../stitch/ISH.bin" + +config IFWI_SENSORS_FW + string "PdtBinary might be needed" + default "../stitch/PdtBinary.bin" + +config IFWI_PDR + string "pdr.bin is optional" + help + "../stitch/pdr.bin" + +# Stitching Tools +config IFWI_INTEL_FIT + string + default "../stitch/fit" + depends on IFWI_STITCH + +config IFWI_INTEL_VSCCOMMN + string + default "../stitch/vsccommn.bin" + depends on IFWI_STITCH + +config IFWI_INTEL_MEU + string + default "../stitch/meu" + depends on IFWI_STITCH + +config IFWI_PRIVATE_KEY + string + default "../stitch/private.pem" + depends on IFWI_STITCH + +config IFWI_BOOTGUARD + bool + default n + depends on IFWI_STITCH + +endif + config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1335090..6f50834 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -189,4 +189,50 @@ cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*) endif +ifeq ($(CONFIG_IFWI_STITCH),y) +# Copy all required files into build dir + +$(obj)/cse_image.bin: + cp $(CONFIG_IFWI_CSE_IMAGE) $@ + +$(obj)/ISH.bin: + cp $(CONFIG_IFWI_ISH_FW) $@ + +$(obj)/INTC_pdt_APL_NS_BOM3_SENSORS: + cp $(CONFIG_IFWI_SENSORS_FW) $@ + +$(obj)/iUnit.bin: + cp $(CONFIG_IFWI_IUNIT) $@ + +$(obj)/pdr.bin: + cp $(CONFIG_IFWI_PDR) $@ + +$(obj)/dsp_fw.bin: + cp $(CONFIG_IFWI_DSP_FW) $@ + +$(obj)/pmcp.bin: + cp $(CONFIG_IFWI_PMCP) $@ + +$(obj)/smip_iafw.bin: + # Create empty smip_iafw.bin with Python + @printf " Generating $@\n" + python -c "import struct; \ + fp = open ('$@', 'wb'); \ + fp.write (b'\xAF\xBE\xED\xDE' + b'\x00' * 0x380 + b'\xAA\xCC\xFF\xAA'); \ + fp.close();" + +$(obj)/fit: + cp $(CONFIG_IFWI_INTEL_FIT) $@ + +$(obj)/vsccommn.bin: + cp $(CONFIG_IFWI_INTEL_VSCCOMMN) $@ + +$(obj)/meu: + cp $(CONFIG_IFWI_INTEL_MEU) $@ + +$(obj)/private.pem: + cp $(CONFIG_IFWI_PRIVATE_KEY) $@ + +endif # CONFIG_IFWI_STITCH + endif # if CONFIG_SOC_INTEL_APOLLOLAKE diff --git a/src/soc/intel/apollolake/stitch/OEMKeyManifest.xml b/src/soc/intel/apollolake/stitch/OEMKeyManifest.xml new file mode 100644 index 0000000..e3dedfa --- /dev/null +++ b/src/soc/intel/apollolake/stitch/OEMKeyManifest.xml @@ -0,0 +1,18 @@ + +<?xml version="1.0" encoding="utf-8"?> +<OEMKeyManifest version="2.11"> + <OemId value="0x0000"/> + <KeyManifestId value="0x1"/> + <VendorId value="0x8086"/> + <SecurityVersionNumber value="0x00000000"/> + <VersionMajor value="0x0000"/> + <VersionMinor value="0x0000"/> + <VersionHotfix value="0x0000"/> + <VersionBuild value="0x0000"/> + <KeyManifestEntries> + <KeyManifestEntry> + <Usage value="IfwiManifest | OemSmipManifest | OemDnxIfwiManifest | BootPolicyManifest"/> + <HashBinary value="build/private_hash.bin"/> + </KeyManifestEntry> + </KeyManifestEntries> +</OEMKeyManifest> diff --git a/src/soc/intel/apollolake/stitch/bios.xml b/src/soc/intel/apollolake/stitch/bios.xml new file mode 100644 index 0000000..af38992 --- /dev/null +++ b/src/soc/intel/apollolake/stitch/bios.xml @@ -0,0 +1,53 @@ + +<?xml version="1.0" encoding="utf-8"?> +<Bios version="2.11"> + <IbbSubPartition label="IBB"> + <Length value="0x0" help_text="Set the length of sub partition."/> + <Usage value="BootPolicyManifest" value_list="CseBupManifest,,CseMainManifest,,PmcManifest,,BootPolicyManifest,,iUnitBootLoaderManifest,,iUnitMainFwManifest,,cAvsImage0Manifest,,cAvsImage1Manifest,,IfwiManifest,,OsBootLoaderManifest,,OsKernelManifest,,OemSmipManifest,,IshManifest,,OemDebugManifest,,SilentLakeVmmManifest,,OemAttestationManifest,,OemDalManifest,,OemDnxIfwiManifest"/> + <VendorId value="0x8086"/> + <SecurityVersionNumber value="0" label="Secure Version Number"/> + <VersionControlNumber value="0" label="Version Control Number"/> + <VersionMajor value="0" label="Version Major"/> + <VersionMinor value="0" label="Version Minor"/> + <VersionHotfix value="0" label="Version Hotfix"/> + <VersionBuild value="0" label="Version Build"/> + <MovePadding value="true" value_list="true,,false" help_text="Move the padding in the partition to be before the first Data-Module and after the CPD header."/> + <VersionExtraction> + <Enabled value="false" value_list="true,,false" help_text="If enabled, the version details will be extracted from the InputFile binary at the offsets specified. If disabled, the version must be specified manually."/> + <InputFile value="" help_text="Binary file from which to extract the version details."/> + <VersionMajorByte0Offset value="0" help_text="Offset of Major Version number's LSB in InputFile."/> + <VersionMajorByte1Offset value="0" help_text="Offset of Major Version number's MSB in InputFile."/> + <VersionMinorByte0Offset value="0" help_text="Offset of Minor Version number's LSB in InputFile."/> + <VersionMinorByte1Offset value="0" help_text="Offset of Minor Version number's MSB in InputFile."/> + <VersionHotfixByte0Offset value="0" help_text="Offset of Hotfix Version number's LSB in InputFile."/> + <VersionHotfixByte1Offset value="0" help_text="Offset of Hotfix Version number's MSB in InputFile."/> + <VersionBuildByte0Offset value="0" help_text="Offset of Build Version number's LSB in InputFile."/> + <VersionBuildByte1Offset value="0" help_text="Offset of Build Version number's MSB in InputFile."/> + </VersionExtraction> + <BootPolicyManifest> + <Enabled value="true" value_list="true,,false" help_text="If set to 'false' the Boot Policy Manifest will not be created and thus the IBB, IBBL and OBB modules will not be covered by the manifest signature."/> + </BootPolicyManifest> + <Modules> + <DataModule name="IBBL"> + <InputFile value="$UserVar1/build/cbfs/fallback/ibbl.rom"/> + </DataModule> + <DataModule name="IBB"> + <InputFile value="$UserVar1/build/cbfs/fallback/ibbm.rom"/> + </DataModule> + </Modules> + </IbbSubPartition> + <ObbSubPartition label="OBB"> + <Length value="0x0" help_text="Set the length of sub partition."/> + <MovePadding value="true" value_list="true,,false" help_text="Move the padding in the partition to be before the first Data-Module and after the CPD header."/> + <Modules> + <DataModule name="OPAD"> + <InputFile value="$UserVar1/build/cbfs/fallback/obb.rom"/> + </DataModule> + </Modules> + <SkipHashModules> + <SkipHashModule> + <Name value="" help_text="Name of the OBB Subpartition Data-Module that will be ignored from hash calculation. Empty name is ignored."/> + </SkipHashModule> + </SkipHashModules> + </ObbSubPartition> +</Bios> diff --git a/src/soc/intel/apollolake/stitch/meu_config.xml.in b/src/soc/intel/apollolake/stitch/meu_config.xml.in new file mode 100644 index 0000000..04186a4 --- /dev/null +++ b/src/soc/intel/apollolake/stitch/meu_config.xml.in @@ -0,0 +1,21 @@ +<?xml version="1.0" encoding="utf-8"?> +<MeuConfig version="2.11"> + <PathVars label="Path Variables"> + <WorkingDir value="./" label="$WorkingDir" help_text="Path for environment variable $WorkingDir"/> + <SourceDir value="./" label="$SourceDir" help_text="Path for environment variable $SourceDir"/> + <DestDir value="./" label="$DestDir" help_text="Path for environment variable $DestDir"/> + <UserVar1 value="./" label="$UserVar1" help_text="Path for environment variable $UserVar1"/> + <UserVar2 value="./" label="$UserVar2" help_text="Path for environment variable $UserVar2"/> + <UserVar3 value="./" label="$UserVar3" help_text="Path for environment variable $UserVar3"/> + </PathVars> + <SigningConfig label="Signing Configuration"> + <SigningTool value="OpenSSL" value_list="Disabled,,OpenSSL,,MobileSigningUtil" label="Signing Tool" help_text="Select tool to be used for signing, or disable signing."/> + <SigningToolPath value="/usr/bin/openssl" label="Signing Tool Path" help_text="Path to signing tool executable."/> + <PrivateKeyPath value="@signing_key@" label="Private Key Path" help_text="Path to private RSA key (in PEM format) to be used for signing. Key is required if using OpenSSL. If using MSU, and value is not-empty, this will override the key in the Signing Tool Config XML."/> + <SigningToolXmlPath value="" label="Signing Tool Config XML Path" help_text="Configuration XML template for MobileSigningUtil. Leave blank if not using MSU."/> + <SigningToolExecPath value="" label="Signing Tool Execution Path" help_text="Specify a directory from which the signing tool should be executed. This can be useful if relative paths are used in the Signing Tool Config XML. If no path is provided, the signing tool will be executed from the same directory as this tool was executed. Leave blank if not using MSU."/> + </SigningConfig> + <CompressionConfig label="Compression Configuration"> + <LzmaToolPath value="" label="LZMA Tool Path" help_text="Path to lzma tool executable."/> + </CompressionConfig> +</MeuConfig> diff --git a/src/soc/intel/apollolake/stitch/spi.xml.in b/src/soc/intel/apollolake/stitch/spi.xml.in new file mode 100644 index 0000000..6f52f26 --- /dev/null +++ b/src/soc/intel/apollolake/stitch/spi.xml.in @@ -0,0 +1,566 @@ +<?xml version="1.0" encoding="utf-8"?> +<FitData version="10.58" sku="@sku@"> + <BuildSettings label="Build Settings"> + <BuildResults label="Image Build Settings"> + <BuildOutputFilename value="coreboot.rom" label="Output Path"/> + <GenIntermediateFiles value="Yes" value_list="No,,Yes" label="Generate Intermediate Files"/> + <BootGrdWrn value="Yes" value_list="No,,Yes" label="Enable Boot Guard warning message at build time"/> + <PTTWrn value="Yes" value_list="No,,Yes" label="Enable Intel (R) Platform Trust Technology warning message at build time"/> + <RegionOrder value="@region@" label="Region Order" help_text="1=IFWI, 4=PDR, 5=TXE Data"/> + <TargetType value="SPI" value_list="eMMC,,UFS,,SPI" label="Target Type" help_text="Select target type. This setting is configurable from the toolbar."/> + <IfwiBuildVersion value="0x0" help_text="32-bit value to use as the IFWI build version number"/> + <MeuToolPath value="" label="Intel(R) Manifest Extension Utility Path"/> + <SigningToolPath value="/usr/bin/openssl" label="Signing Tool Path"/> + <SigningTool value="OpenSSL" value_list="OpenSSL,,MobileSigningUtil" label="Signing Tool"/> + <VerifySigningKeysAgainstOemKeyManifest value="Yes" value_list="No,,Yes" label="Verify manifset signing keys against the OEM Key Manifest." help_text="Indicates whether or not FIT should verify that the OEM Key Manifest contains the hash of the public keys used for signing sub-partitions provided by the OEM."/> + </BuildResults> + <PathVars label="Environment Variables"> + <WorkingDir value="." label="$WorkingDir" help_text="Path for environment variable $WorkingDir"/> + <SourceDir value="." label="$SourceDir" help_text="Path for environment variable $SourceDir"/> + <DestDir value="." label="$DestDir" help_text="Path for environment variable $DestDir"/> + <UserVar1 value="." label="$UserVar1" help_text="Path for environment variable $UserVar1"/> + <UserVar2 value="." label="$UserVar2" help_text="Path for environment variable $UserVar2"/> + <UserVar3 value="." label="$UserVar3" help_text="Path for environment variable $UserVar3"/> + </PathVars> + </BuildSettings> + <FlashLayout label="Flash Layout"> + <SubPartitions> + <SmipSubPartition label="SMIP Sub-Partition"> + <IaFwSmipInputFile value="$SourceDir/build/smip_iafw.bin" label="IAFW SMIP Binary File"/> + </SmipSubPartition> + <IunitSubPartition label="IUnit Sub-Partition"> + <InputFile value="" label="IUnit Binary File" help_text="This loads the IUnit binary that will be merged into the output image generated by Intel(R) FIT tool." /> + </IunitSubPartition> + <PmcSubPartition label="PMC Sub-Partition"> + <InputFile value="$SourceDir/build/pmcp.bin" label="PMC Binary File" help_text="This loads the PMC binary that will be merged into the output image generated by Intel(R) FIT tool."/> + </PmcSubPartition> + <UCodeSubPartition label="uCode Sub-Partition"> + <UCodePatch1InputFile value="@patch1@" label="uCode Patch 1 Input File" help_text="This loads the uCode Patch 1 binary that will be merged into the output image generated by Intel(R) FIT tool."/> + <UCodePatch2InputFile value="@patch2@" label="uCode Patch 2 Input File" help_text="This loads the uCode Patch 2 binary that will be merged into the output image generated by Intel(R) FIT tool."/> + </UCodeSubPartition> + <TXESubPartition label="Intel(R) TXE Sub-Partition"> + <InputFile value="$SourceDir/build/cse_image.bin" label="Intel(R) TXE Binary File" help_text="This loads the Intel (R) TXE binary that will be merged into the output image generated by the Intel(R) FIT tool."/> + </TXESubPartition> + <BiosSubPartition label="IAFW/BIOS Sub-Partition"> + <InputFile value="$SourceDir/build/bios.bin" label="IAFW/BIOS Binary File" help_text="This loads the IAFW/BIOS binary that will be merged into the output image generated by Intel(R) FIT tool."/> + <EnableSplitObb value="No" value_list="No,,Yes" label="Enable Split OBB" help_text="Set to Yes to allow OBB to be split between Boot Partitions. The first portion of OBB will be placed in Boot Partition 1, and the remaining in Boot Partition 2 if the component does not fit in a single boot partition."/> + <BiosDataSize value="512KB" value_list="512KB,,384KB,,256KB,,128KB,,0" label="Bios Data Size" help_text="Configures the BIOS data size in SPI target configurations."/> + </BiosSubPartition> + <PdrRegion label="SPI PDR Region"> + <Length value="0" /> + <InputFile value="" label="PDR Binary File" help_text="This loads the Platform Data Sub-Partition binary that will be merged into the into the output image generated by the Intel(R) FIT tool." /> + <Enabled value="Disabled" value_list="Disabled,,Enabled" label="PDR Region Enable" help_text="This option allows the user to enable or disable the Platform Data Region. This setting is only applicable for SPI images." /> + </PdrRegion> + <EcRegion label="SPI EC Region"> + <Length value="0" /> + <InputFile value="" label="EC Binary File" help_text="This loads the Embedded Controller binary used for eSPI that will be merged into the output image generated by the Intel(R) FIT tool." /> + <Enabled value="Disabled" value_list="Disabled,,Enabled" label="EC Region Enable" help_text="This option allows the user to enable or disable the Embedded Controller Data Region. This setting is only applicable for SPI images." /> + <EcRegionPointer value="" label="EC Region Pointer File" help_text="This loads a binary containing the 16 byte value to be written in the Embedded Controller Pointer region." /> + </EcRegion> + </SubPartitions> + </FlashLayout> + <FlashSettings label="Flash Settings"> + <FlashComponents label="Flash Components"> + <NumberOfComponents value="1" value_list="1,,2" label="Number of Flash Components" help_text="Specifies the number of Flash components that will be installed on the target machine if using SPI. For eMMC and UFS, this represents the number of boot partitions and is fixed at 2,For SPI, this is fixed at 1." /> + <FlashComponent1Size value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" label="Flash component 1 Size" help_text="This field identifies the size of the 1st Flash component if using SPI. This represents the size of the first boot partition if using eMMC/UFS." /> + <FlashComponent2Size value="8MB" value_list="512KB,,1MB,,2MB,,4MB,,8MB,,16MB,,32MB,,64MB" label="Flash component 2 Size" help_text="This field identifies the size of the 2nd Flash component if using SPI. This represents the size of the second boot partition if using eMMC/UFS and will be equal to the first boot partition size." /> + <BiosRegionOverlap value="false" value_list="true,,false" label="Bios Region Overlap" help_text="Overlap Bios and ME regions in SPI mode." /> + </FlashComponents> + <BootSourceSelection label="Boot Source Selection"> + <SpiBootSourceEnabled value="Enabled" value_list="Enabled,,Disabled" label="SPI Boot Source Enable/Disable" help_text="Permanent Enable/Disable SPI Boot Device FPF" /> + <UfsBootSourceEnabled value="Disabled" value_list="Enabled,,Disabled" label="UFS Boot Source Enable/Disable" help_text="Permanent Enable/Disable UFS Boot Device FPF" /> + <EmmcBootSourceEnabled value="Disabled" value_list="Enabled,,Disabled" label="eMMc Boot Source Enable/Disable" help_text="Permanent Enable/Disable eMMc Boot Device FPF" /> + </BootSourceSelection> + <UfsSettings label="UFS Settings"> + <UfsPhyBinary value="" label="UFS Phy Init Binary" help_text="UFS PHY Binary sub-partiion. Maximum size is 1 KB" /> + <UfsGppLunEnabled value="Disabled" value_list="Disabled,,Enabled" label="UFS GPP LUN Enable" help_text="Set to 'Enabled' to enable UFS GPP LUN Sub-Partition" /> + <UfsGppLunId value="6" value_list="0,,1,,2,,3,,4,,5,,6,,7" label="UFS GPP LUN ID" help_text="The UFS GPP LUN ID is a single byte value stored in the UFS GPP LUN Sub-Partition" /> + </UfsSettings> + <HostCpuBiosMasterAccess label="Host CPU / BIOS Master Access"> + <HostCpuWriteAccess value="0xFFF" value_list="0xFFF,,0x112,,0x002,,0x102,,0x012,,Custom" label="Host CPU / BIOS Write Access" help_text="This setting determines write access control for the Host CPU / BIOS. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + <HostCpuWriteAccessCustom value="0x0" label="Host CPU / BIOS Write Access Custom" help_text="This setting determines write access control for the Host CPU / BIOS. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + <HostCpuReadAccess value="0xFFF" value_list="0xFFF,,0x013,,0x103,,0x003,,0x113,,Custom" label="Host CPU / BIOS Read Access" help_text="This setting determines read access control for the Host CPU / BIOS. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + <HostCpuReadAccessCustom value="0x0" label="Host CPU / BIOS Read Access Custom" help_text="This setting determines read access control for the Host CPU / BIOS. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + </HostCpuBiosMasterAccess> + <IntelTxeMasterAccess label="Intel(R) TXE Master Access"> + <TxeWriteAccess value="0xFFF" value_list="0xFFF,,0x024,,Custom" label="Intel(R) TXE Write Access" help_text="This setting determines write access control for the TXE. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + <TxeWriteAccessCustom value="0x0" label="Intel(R) TXE Write Access Custom" help_text="This setting determines write access control for the TXE. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + <TxeReadAccess value="0xFFF" value_list="0xFFF,,0x027,,Custom" label="Intel(R) TXE Read Access" help_text="This setting determines read access control for the TXE. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + <TxeReadAccessCustom value="0x0" label="Intel(R) TXE Read Access Custom" help_text="This setting determines read access control for the TXE. For further details on Region Access Control see the SPI and SMIP Programming Guide" /> + </IntelTxeMasterAccess> + <EcMasterAccess label="EC Master Access"> + <EcWriteAccess value="0xFFF" value_list="0xFFF,,0x100,,Custom" label="Embedded Controller Write Access" help_text="This setting determines write access control for the Embedded Controller region. For further details on Region Access Control see Skylake H / LP SPI Programming guide." /> + <EcWriteAccessCustom value="0x0" label="Embedded Controller Write Access Custom" help_text="This setting determines write access control for the Embedded Controller region. For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." /> + <EcReadAccess value="0xFFF" value_list="0xFFF,,0x101,,Custom" label="Embedded Controller Read Access" help_text="This setting determines read access control for the Embedded Controller region. For further details on Region Access Control see Skylake H / LP SPI Programming guide." /> + <EcReadAccessCustom value="0x0" label="Embedded Controller Read Access Custom" help_text="This setting determines read access control for the Embedded Controller region. For further details on Region Access Control see Canonlake H / LP SPI Programming guide further details." /> + </EcMasterAccess> + <FlashConfiguration label="Flash Configuration"> + <BootBlockSize value="64KB" value_list="64KB,,128KB,,256KB,,512KB,,1MB" label="Boot Block Size" help_text="This soft strap only applies when booting from SPI. Boot from LPC (FWH) only supports a 64KB boot block size (Invert A16) and this soft strap value is a don't care. Note No bits are inverted if a Reserved encoding is programmed." /> + <SpiDualIoReadEnable value="No" value_list="No,,Yes" label="Dual I/O Read Enable" help_text="This soft-strap only has effect if Dual I/O Read is discovered as supported via the SFDP." /> + <DualOutFastReadSupport value="No" value_list="No,,Yes" label="Dual Output Fast Read Supported" help_text="This setting allows customers to configure if Dual Output Fast Read is supported. See SPI and SMIP Programming guide further details." /> + <SpiDualOutReadEnable value="No" value_list="No,,Yes" label="Dual Output Read Enable" help_text="This soft-strap only has effect if Dual Output Read is discovered as supported via the SFDP. If parameter table is not detected via the SFDP, this bit has no effect and Dual Output Read is controlled via the Flash Descriptor.Component Section.Dual Output Fast Read Support bit." /> + <FastReadClockFreq value="50MHz" value_list="50MHz,,40MHz,,25MHz" label="Fast Read Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Fast Read. See SPI and SMIP Programming guide further details." /> + <EcMaxFreq value="50MHz" value_list="17MHz,,20MHz,,25MHz,,40MHz,,50MHz" label="EC Max Frequency" help_text="This setting allows customers to configure the EC maximum frequency setting for Fast Read. See SPI and SMIP Programming guide further details." /> + <FastReadSupport value="Yes" value_list="No,,Yes" label="Fast Read Supported" help_text="This setting allows customers to enable support for Fast Read capabilities for flash components. See SPI and SMIP Programming guide further details. Note: This setting needs to be enabled when using Dual / Quad enabled components." /> + <SpiVoltageValue value="1.8V" value_list="3.3V,,1.8V" label="SPI Buffer 1p8volt Select" help_text="This strap sets the internal control signal on the pad for either 1.8 or 3.3 V operation." /> + <EcMaxIoMode value="Single IO Mode" value_list="Single IO Mode,,Single and Dual IO Mode,,Single and Quad IO Mode,,Single, Dual and Quad I/O" label="EC Max IO Mode" help_text="Indicates the maximum IO Mode (Single/Dual/Quad) of the eSPI bus that is supported by the eSPI Master and specific platform configuration. The actual IO Mode of the eSPI bus will be the minimum of this field and the Slave's maximum IO Mode advertised in its General Capabilities register." /> + <InvalidInstruction0 value="0x00000021" label="Invalid Instruction 0" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction1 value="0x00000042" label="Invalid Instruction 1" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction2 value="0x00000060" label="Invalid Instruction 2" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction3 value="0x000000AD" label="Invalid Instruction 3" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction4 value="0x000000B7" label="Invalid Instruction 4" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction5 value="0x000000B9" label="Invalid Instruction 5" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction6 value="0x000000C4" label="Invalid Instruction 6" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <InvalidInstruction7 value="0x000000C7" label="Invalid Instruction 7" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." /> + <PrrTopSwapOverride value="No" value_list="No,,Yes" label="Protected Range and Top Swap Override" help_text="For more information, see SPI and SMIP Programming Guide" /> + <QuadIoReadEnable value="Yes" value_list="No,,Yes" label="Quad I/O Read Enable" help_text="This soft-strap only has effect if Quad I/O Read is discovered as supported via the SFDP." /> + <QuadOutReadEnable value="No" value_list="No,,Yes" label="Quad Output Read Enable" help_text="This soft-strap only has effect if Quad Output Read is discovered as supported via the SFDP." /> + <ReadIdAndReadStatClkFreq value="50MHz" value_list="50MHz,,40MHz,,25MHz" label="Read ID and Read Status Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Read ID and Read Status. See SPI and SMIP Programming guide further details." /> + <SpiStopPrefetchonFlushPending value="No" value_list="No,,Yes" label="SPI Stop Prefetch on Flush Pending" help_text="This soft-strap determines the reset t value of the BIOS Flash Program Register AFC.SPFP bit." /> + <SpiHostSwSequencingEnableDefault value="No" value_list="No,,Yes" label="SPI Host Software Sequencing Enable Default" help_text="This strap sets the default value of the CSME ICE.HSSEN register." /> + <SpiEnableDevice0DeepPowerdown value="No" value_list="No,,Yes" label="SPI Enable Device 0 Deep Powerdown" /> + <SpiEnableDevice1DeepPowerdown value="No" value_list="No,,Yes" label="SPI Enable Device 1 Deep Powerdown" /> + <SpiDelayBeforeRPMCBusyPollEnable value="No" value_list="No,,Yes" label="SPI Enable Delay before RPMC busy poll" /> + <SpiDelayBeforeEraseBusyPollEnable value="No" value_list="No,,Yes" label="SPI Enable Delay before erase busy poll" /> + <SpiDelayBeforeWriteBusyPollEnable value="No" value_list="No,,Yes" label="SPI Enable Delay before write busy poll" /> + <SpiIdletoDeepPowerDownTimeoutDefault value="0x00000005" label="SPI Idle to Deep Power Down Timeout Default" help_text="Specifies the time in microseconds that the Flash Controller waits after all activity is idle before commanding the flash devices to Deep Powerdown. Max is 2^15 = 32768." /> + <WriteEraseClockFreq value="50MHz" value_list="50MHz,,40MHz,,25MHz" label="Write and Erase Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Write and Erase. See SPI and SMIP Programming guide further details." /> + <WriteProtectionEnable value="No" value_list="No,,Yes" label="Write Protection Enable" help_text="Base/limit are inclusive" /> + <ProtectedRangeLimit value="0x00000000" label="Protected Range Limit" help_text="This field corresponds to FLA (Flash Linear Address) address bits 26:12 and specifies the upper limit of the protected range. Address bits 11:0 are assumed to be FFFh for the limit comparison. Any address greater than the value programmed in this field is unaffected by this protected range. Note: If either Write or Read protection is enabled, then Limit must be configured greater than or equal to Base. See SPI and SMIP Programming Guide for more information." /> + <ReadProtectionEnable value="No" value_list="No,,Yes" label="Read Protection Enable" help_text="Base/limit are inclusive" /> + <ProtectedRangeBase value="0x00000000" label="Protected Range Base" help_text="This field corresponds to FLA (Flash Linear Address) address bits 26:12 and specifies the lower base of the protected range. Address bits 11:0 are assumed to be 000h for the base comparison. Any address less than the value programmed in this field is unaffected by this protected range. Note: Note: If either Write or Read protection is enabled, then Limit must be configured greater than or equal to Base. See SPI and SMIP Programming Guide for more details." /> + <SpiResumeHoldoffDelay value="8us" value_list="0us,,2us,,4us,,6us,,8us,,10us,,12us,,14us" label="SPI Resume Hold off Delay - tRHD" help_text="Resume Holdoff Delay (tRHD) Specifies the time after the completion of a pri_op before the flash controller sends the resume instruction. If a new pri_op is eligible to be issued prior to the end of this delay time then the pri_op is issued and the timer is re-initialized to tRHD." /> + <SpiSuspendResumeDisable value="Yes" value_list="No,,Yes" label="SPI Suspend Resume Disable" help_text="Chicken bit to disable sending a pri_op to a flash device that is busy. The pri_op may still be issued to a different device." /> + <SpiResumeToSuspendCeiling value="no ceiling, use the SFDP values" value_list="128us,,256us,,512us,,no ceiling, use the SFDP values" label="SPI Resume to Suspend Ceiling " help_text="Specifies at maximum value for the write and erase Resume to Suspend intervals" /> + </FlashConfiguration> + <VsccTable label="VSCC Table"> + <VsccEntries label="VSCC Entries"> + <VsccEntry label="VSCC Entry"> + <VsccEntryName value="VsccEntry0" label="Part Name"/> + <VsccEntryVendorId value="0x1F" label="Vendor ID"/> + <VsccEntryDeviceId0 value="0x47" label="Device ID 0"/> + <VsccEntryDeviceId1 value="0x00" label="Device ID 1"/> + </VsccEntry> + <VsccEntry label="VSCC Entry"> + <VsccEntryName value="W25Q64DW" label="Part Name"/> + <VsccEntryVendorId value="0xEF" label="Vendor ID"/> + <VsccEntryDeviceId0 value="0x60" label="Device ID 0"/> + <VsccEntryDeviceId1 value="0x17" label="Device ID 1"/> + </VsccEntry> + <VsccEntry label="VSCC Entry"> + <VsccEntryName value="GD25LQ64" label="Part Name"/> + <VsccEntryVendorId value="0xC8" label="Vendor ID"/> + <VsccEntryDeviceId0 value="0x60" label="Device ID 0"/> + <VsccEntryDeviceId1 value="0x17" label="Device ID 1"/> + </VsccEntry> + <VsccEntry label="VSCC Entry"> + <VsccEntryName value="W25Q128FW" label="Part Name"/> + <VsccEntryVendorId value="0xEF" label="Vendor ID"/> + <VsccEntryDeviceId0 value="0x60" label="Device ID 0"/> + <VsccEntryDeviceId1 value="0x18" label="Device ID 1"/> + </VsccEntry> + <VsccEntry label="VSCC Entry"> + <VsccEntryName value="MX25U6473F" label="Part Name"/> + <VsccEntryVendorId value="0xC2" label="Vendor ID"/> + <VsccEntryDeviceId0 value="0x25" label="Device ID 0"/> + <VsccEntryDeviceId1 value="0x37" label="Device ID 1"/> + </VsccEntry> + </VsccEntries> + </VsccTable> + </FlashSettings> + <CpuStraps label="CPU Straps"> + <PUnit label="PUNIT"> + <ThermalThrottleUnlock value="Locked" value_list="Locked,,Unlocked" label="Thermal Throttle Unlock" help_text="See SPI and SMIP Programming Guide for more information" /> + <ExtendedReliabilityEnable value="Disabled" value_list="Disabled,,Enabled" label="Extended Reliability Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <SoftSvidEnable value="Enabled" value_list="Enabled,,Disabled" label="Soft SVID Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <Rail0AlertPollEnable value="Enabled" value_list="Disabled,,Enabled" label="Rail 0 Alert Polling Enable" help_text="This bit defines whether the STATUS1 register for Rail 0 must be polled on Alert# assertions or not." /> + <Rail0SvidId value="0x00000000" label="Rail 0 SVID ID" help_text="This contains the PMIC Rail ID for SVID Rail 0, i.e. Vccgi. PCODE uses this to program the SVID_RAIL0_CONFIG_AND_STATUS register during reset." /> + <Rail1AlertPollEnable value="Enabled" value_list="Disabled,,Enabled" label="Rail 1 Alert Polling Enable" help_text="This bit defines whether the STATUS1 register for Rail 1 must be polled on Alert# assertions or not." /> + <Rail1SvidId value="0x00000002" label="Rail 1 SVID ID" help_text="This contains the PMIC Rail ID for SVID Rail 1, aka Vnn. PCODE uses this to program the SVID_RAIL1_CONFIG_AND_STATUS register during reset." /> + </PUnit> + </CpuStraps> + <FlexIo label="Flex I/O"> + <ModPhyLaneConfiguration> + <ModPhyLane2 value="USB3" value_list="USB3,,PCIe" /> + <ModPhyLane3 value="USB3" value_list="USB3,,PCIe" /> + <ModPhyLane4 value="USB3" value_list="USB3,,PCIe" /> + <ModPhyLane8 value="SATA" value_list="USB3,,SATA" /> + </ModPhyLaneConfiguration> + <UsbX label="USBx"> + <Usb3SsicPort1Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 1 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicPort2Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 2 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicPort3Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 3 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicPort4Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 4 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicPort5Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 5 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicPort6Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 6 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicPort7Ownership value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Port 7 Ownership" help_text="See SPI and SMIP Programming Guide for more information" /> + </UsbX> + <Exi label="EXI"> + <Usb3SsicComboPort1 value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Combo Port 1" help_text="See SPI and SMIP Programming Guide for more information" /> + <Usb3SsicComboPort2 value="USB3" value_list="USB3,,SSIC" label="USB3/SSIC Combo Port 2" help_text="See SPI and SMIP Programming Guide for more information" /> + <UfsComboPort0 value="non-UFS" value_list="non-UFS,,UFS" label="UFS Combo Port 0" help_text="See SPI and SMIP Programming Guide for more information" /> + <PcieUsb3ComboPort0 value="USB3" value_list="USB3,,PCIe" label="PCIe/USB3 Combo Port 0" help_text="See SPI and SMIP Programming Guide for more information" /> + <PcieUsb3ComboPort1 value="USB3" value_list="USB3,,PCIe" label="PCIe/USB3 Combo Port 1" help_text="See SPI and SMIP Programming Guide for more information" /> + <PcieUsb3ComboPort2 value="USB3" value_list="USB3,,PCIe" label="PCIe/USB3 Combo Port 2" help_text="See SPI and SMIP Programming Guide for more information" /> + <PcieUsb3ComboPort3 value="USB3" value_list="USB3,,PCIe" label="PCIe/USB3 Combo Port 3" help_text="See SPI and SMIP Programming Guide for more information" /> + </Exi> + <Fia label="FIA"> + <StaggeringEnable value="Enabled" value_list="Disabled,,Enabled" label="Staggering Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + </Fia> + <PcieX2 label="PCIe (x2)"> + <PcieRootPortConfig value="2x1" value_list="2x1,,1x2" label="Root Port Configuration (RPCFG)" /> + <PcieLaneReversal value="No" value_list="No,,Yes" label="Lane Reversal (LNREV)" /> + <PciePort0NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 0 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <PciePort1NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 1 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <PciePort2NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 2 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <PciePort3NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 3 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + </PcieX2> + <PcieX4 label="PCIe (x4)"> + <PcieRootPortConfig value="4x1" value_list="4x1,,1x2, 2x1,,2x2,,1x4" label="Root Port Configuration (RPCFG)" /> + <PcieLaneReversal value="No" value_list="No,,Yes" label="Lane Reversal (LNREV)" /> + <PciePort0NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 0 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <PciePort1NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 1 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <PciePort2NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 2 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + <PciePort3NonCmnClockSscMode value="Disabled" value_list="Disabled,,Enabled" label="PCIe Port 3 Non-Common Clock With SSC Mode Enable" help_text="See SPI and SMIP Programming Guide for more information" /> + </PcieX4> + <Sata label="SATA"> + <MPhyLaneSataPort0 value="SATA" value_list="SATA,,PCIe,,GPIO" label="Mod-PHY lane SATA Port 0" help_text="See SPI and SMIP Programming Guide for more information" /> + <MPhyLaneSataPort1 value="SATA" value_list="SATA,,PCIe,,GPIO" label="Mod-PHY lane SATA Port 1" help_text="This configuration is auto-populated according to the value of the modphylane8 configuration as this signal is multiplexed with USB3 Port-5 signal. See SPI and SMIP Programming Guide for more information" /> + <SataPcieGpioPolarityPort0 value="0 = PCIe" value_list="0 = PCIe,,0 = SATA" label="SATA/PCIe Select GPIO polarity for SATA Port 0" help_text="See SPI and SMIP Programming Guide for more information" /> + <SataPcieGpioPolarityPort1 value="0 = PCIe" value_list="0 = PCIe,,0 = SATA" label="SATA/PCIe Select GPIO polarity for SATA Port 1" help_text="See SPI and SMIP Programming Guide for more information" /> + </Sata> + </FlexIo> + <PlatformConfiguration label="Platform Configuration"> + <PmicVrConfig value="0x3" value_list="SVID VR - Discrete SVID,,I2C VR - Anpec APW8858,,I2C VR - RT DS5077,,I2C VR - Rohm BD2671MVW" label="PMIC/VR Configuration" help_text="These are the supported VR types for GLK SOC. Intel FW only supports this BOM list." /> + <PrtcBackupPower value="Exists" value_list="None,,Exists" label="Persistent PRTC Backup Power" help_text="FPF that indicates if the device is designed such that it may lose PRTC power more than 10 times throughout the normal lifecycle of the product and hence has no persistent time or AR protection. At EOM, this value is burned to an FPF, and can never be changed" /> + <SMIP_VERSION_CATEGORY label="SMIP Version Config"> + <PMC_OEM_SMIP_VERSION.MAJOR_VERSION value="0x00000000" help_text="Version information for the PMC OEM SMIP. Used internally by PMC FW team to communicate which SMIP version is in use. OEMs and other users of the SMIP can use this field to identify a version. " /> + <PMC_OEM_SMIP_VERSION.CONFIG_VERSION value="0x00000000" help_text="Version information for the PMC OEM SMIP. Used internally by PMC FW team to communicate which SMIP version is in use. OEMs and other users of the SMIP can use this field to identify a version. " /> + <PMC_OEM_SMIP_VERSION.MINOR_VERSION value="0x00000000" help_text="Version information for the PMC OEM SMIP. Used internally by PMC FW team to communicate which SMIP version is in use. OEMs and other users of the SMIP can use this field to identify a version. " /> + <PMC_OEM_SMIP_VERSION.ENGR_VERSION value="0x00000000" help_text="Version information for the PMC OEM SMIP. Used internally by PMC FW team to communicate which SMIP version is in use. OEMs and other users of the SMIP can use this field to identify a version. " /> + </SMIP_VERSION_CATEGORY> + <POWER_DELIVERY_CATEGORY label="Platform Power Delivery Config"> + <POWER_DELIVERY.DDR_PHY_RAIL_OPTION value="DDR_PHY_VCCRAM" value_list="DDR_PHY_VCCRAM,,DDR_PHY_VNN" help_text="Platform Power Delivery Options." /> + <POWER_DELIVERY.FIXED_VNN_VR value="VID_VNN_VR" value_list="VID_VNN_VR,,FIXED_VNN_VR" help_text="Platform Power Delivery Options." /> + </POWER_DELIVERY_CATEGORY> + <I2CVR_CATEGORY label="I2C VR Config"> + <IAI2CVRRdWrInValidAddrRange_0.IAI2CVRRdWrInValidAddrRange_0 value="0x5E275E00" help_text="This field only applicable and programmable if there is an I2C VR attached on the platform. Note that there are 32 of these such registers, IAI2CVRRdWrInValidAddrRange[32:0]. List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_1.IAI2CVRRdWrInValidAddrRange_1 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_2.IAI2CVRRdWrInValidAddrRange_2 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_3.IAI2CVRRdWrInValidAddrRange_3 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_4.IAI2CVRRdWrInValidAddrRange_4 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_5.IAI2CVRRdWrInValidAddrRange_5 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_6.IAI2CVRRdWrInValidAddrRange_6 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + <IAI2CVRRdWrInValidAddrRange_7.IAI2CVRRdWrInValidAddrRange_7 value="0x00000000" help_text="List of register ranges in I2C voltage regulator which are subject to write access control. I2CVR addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate I2CVR base address 0x12, offset 0x34 to I2CVR base address 0x56, offset 0x78 are inaccessible.. " /> + </I2CVR_CATEGORY> + <PLL_CATEGORY label="LJ1PLL and LCPLL Config"> + <LJ1PLL_SETTINGS_FORCE_COLD_RESET.LJ1PLL_SETTINGS_FORCE_COLD_RESET value="DISABLE" value_list="DISABLE,,ENABLE" help_text="LJ1PLL settings will force a cold reset when this is non-zero. Normal usage is to force a cold reset (assert this bit) if changes to LJ1PLL are desired, otherwise BIOS is expected to cause a cold reset for LJ1PLL changes to take effect." /> + <LJ1PLL_RW_CONTROL_1_DEFAULT.SSC_EN value="DISABLE" value_list="DISABLE,,ENABLE" help_text="LJ1PLL_RW_CONTROL_1 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_1_DEFAULT.SSC_EN_OVR value="DISABLE_OVERRIDE" value_list="DISABLE_OVERRIDE,,ENABLE_OVERRIDE" help_text="LJ1PLL_RW_CONTROL_1 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_2_DEFAULT.SSC_FRAC_STEP value="0x00007D9C" help_text="LJ1PLL_RW_CONTROL_2 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_2_DEFAULT.SSC_MODE value="DOWN_SPREAD_ONLY" value_list="DOWN_SPREAD_ONLY,,UP_SPREAD_ONLY,,CENTER_SPREAD_START_W_DOWN_SPREAD,,CENTER_SPREAD_START_W_UP_SPREAD" help_text="LJ1PLL_RW_CONTROL_2 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_2_DEFAULT.SSC_CYC_TO_PEAK_M1 value="0x0000012B" help_text="LJ1PLL_RW_CONTROL_2 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_5_DEFAULT.PLL_RATIO_INT value="0x0000007D" help_text="LJ1PLL_RW_CONTROL_5 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_5_DEFAULT.PLL_RATIO_FRAC value="0x00000000" help_text="LJ1PLL_RW_CONTROL_5 register default value to be programmed during boot. " /> + <LCPLL_RW_CONTROL_1_DEFAULT.SSC_EN value="DISABLE" value_list="DISABLE,,ENABLE" help_text="LCPLL_RW_CONTROL_1 register default value to be programmed during boot - highly recommended not to change these fields as they are related to high-speed IOs. " /> + <LCPLL_RW_CONTROL_1_DEFAULT.SSC_EN_OVR value="DISABLE_OVERRIDE" value_list="DISABLE_OVERRIDE,,ENABLE_OVERRIDE" help_text="LCPLL_RW_CONTROL_1 register default value to be programmed during boot - highly recommended not to change these fields as they are related to high-speed IOs. " /> + <LCPLL_RW_CONTROL_2_DEFAULT.SSC_FRAC_STEP value="0x00007D9C" help_text="LCPLL_RW_CONTROL_2 register default value to be programmed during boot - highly recommended not to change these fields as they are related to high-speed IOs. " /> + <LCPLL_RW_CONTROL_2_DEFAULT.SSC_MODE value="DOWN_SPREAD_ONLY" value_list="DOWN_SPREAD_ONLY,,UP_SPREAD_ONLY,,CENTER_SPREAD_START_W_DOWN_SPREAD,,CENTER_SPREAD_START_W_UP_SPREAD" help_text="LCPLL_RW_CONTROL_2 register default value to be programmed during boot - highly recommended not to change these fields as they are related to high-speed IOs. " /> + <LCPLL_RW_CONTROL_2_DEFAULT.SSC_CYC_TO_PEAK_M1 value="0x0000012B" help_text="LCPLL_RW_CONTROL_2 register default value to be programmed during boot - highly recommended not to change these fields as they are related to high-speed IOs. " /> + <LJ1PLL_RW_CONTROL_2_DEFAULT_2000.SSC_FRAC_STEP value="0x000068AD" help_text="LJ1PLL_RW_CONTROL_2 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_2_DEFAULT_2000.SSC_MODE value="DOWN_SPREAD_ONLY" value_list="DOWN_SPREAD_ONLY,,UP_SPREAD_ONLY,,CENTER_SPREAD_START_W_DOWN_SPREAD,,CENTER_SPREAD_START_W_UP_SPREAD" help_text="LJ1PLL_RW_CONTROL_2 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_2_DEFAULT_2000.SSC_CYC_TO_PEAK_M1 value="0x0000012B" help_text="LJ1PLL_RW_CONTROL_2 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_5_DEFAULT_2000.PLL_RATIO_INT value="0x00000068" help_text="LJ1PLL_RW_CONTROL_5 register default value to be programmed during boot. " /> + <LJ1PLL_RW_CONTROL_5_DEFAULT_2000.PLL_RATIO_FRAC value="0x002AAAAB" help_text="LJ1PLL_RW_CONTROL_5 register default value to be programmed during boot. " /> + </PLL_CATEGORY> + <MISC_CATEGORY label="MISC Config"> + <TCO_NO_REBOOT.TCO_NO_REBOOT value="REBOOT" value_list="REBOOT,,NO_REBOOT" help_text="GCR.PMC_CFG.NO_REBOOT configuration. 1'b0 = reboot, 1'b1 = no_reboot. Disabling of TCO_NO_REBOOT is required for resetbreak to occur when handling reset from TCO source.. TCO is a software-controlled platform-level watchdog timer" /> + <RESETBUTTON_DEBOUNCE_DIS.RESETBUTTON_DEBOUNCE_DIS value="ENABLE_DEBOUNCE" value_list="ENABLE_DEBOUNCE,,DISABLE_DEBOUNCE" help_text="Value to be programmed for the HW bit to disable the reset button debounce circuit. Debounce the circuit may be required depending on reset button hardware" /> + <S0IX_VR_RAMP_TIMER.S0IX_VR_RAMP_TIMER value="0xA0" help_text="Default value to write to VNNAON_LDO_CTL.S0IX_VR_RAMP_TIMER PMU register field. RTC clock timer value for Vnn/Vccram rail ramp during S0ix exit. The default value of 0hA0 corresponds to 5.12 ms. A value of 0x01 would correspond to 32 us. 0x01: 32 us, 0x02: 64 us, 0xA0: 5.12 ms. Precision is 32e-6.. " /> + <MISC_PMC_ENABLE.ALLOW_I2C_CONNECTION_WITH_SVID value="DO_NOT_ALLOW_I2C_CONNECTION_WITH_SVID" value_list="DO_NOT_ALLOW_I2C_CONNECTION_WITH_SVID,,ALLOW_I2C_CONNECTION_WITH_SVID" help_text="PMC Feature enable bits. " /> + <MISC_PMC_ENABLE.FUNC_DIS_RTC_SAVE_ENABLE value="ENABLE_FUNC_DIS_RTC_SAVE" value_list="DISABLE_FUNC_DIS_RTC_SAVE,,ENABLE_FUNC_DIS_RTC_SAVE" help_text="PMC Feature enable bits. " /> + <SX_EMMC_RST_ASSERTION_OVRD.S5_EMMC_RST_ASSERTION_OVRD value="OVERRIDE_DISABLE" value_list="OVERRIDE_DISABLE,,OVERRIDE_ENABLE" help_text="Force EMMC_RST assertion on Sx entry. Override to enable EMMC_RST assertion on S5 entry" /> + <SX_EMMC_RST_ASSERTION_OVRD.S3_EMMC_RST_ASSERTION_OVRD value="OVERRIDE_DISABLE" value_list="OVERRIDE_DISABLE,,OVERRIDE_ENABLE" help_text="Force EMMC_RST assertion on Sx entry. Override to enable EMMC_RST assertion on S3 entry" /> + <SUS_STAT_DEASSERT_TIME.SUS_STAT_DEASSERT_TIME value="0x00000000" help_text="Minimum time guaranteed to be elapsed before SUS_STAT deassertion. Note this feature not available in BXTp-A0; available BXTp-B0 and beyond.. Note this feature not available in BXTp-A0; available BXTp-B0 and beyond." /> + </MISC_CATEGORY> + <WHISKEYCOVE_CATEGORY label="Whiskey Cove Config"> + <IASecureRdWrInValidAddrRange_0.IASecureRdWrInValidAddrRange_0 value="0x4E924E92" help_text="Note that there are 32 of these such registers, IASecureRdWrInvalidAddrRange[32:0]. Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_1.IASecureRdWrInValidAddrRange_1 value="0x4FCB4FB5" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_2.IASecureRdWrInValidAddrRange_2 value="0x5E305E30" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_3.IASecureRdWrInValidAddrRange_3 value="0x5E615E3C" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_4.IASecureRdWrInValidAddrRange_4 value="0x5E6B5E66" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_5.IASecureRdWrInValidAddrRange_5 value="0x5FAD5FAC" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_6.IASecureRdWrInValidAddrRange_6 value="0x6F356F00" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_7.IASecureRdWrInValidAddrRange_7 value="0x6FDB6FD0" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_8.IASecureRdWrInValidAddrRange_8 value="0x6FE36FDD" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_9.IASecureRdWrInValidAddrRange_9 value="0x1A0A1A07" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_10.IASecureRdWrInValidAddrRange_10 value="0x120A1207" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_11.IASecureRdWrInValidAddrRange_11 value="0x140A1407" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_12.IASecureRdWrInValidAddrRange_12 value="0x1C361C35" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_13.IASecureRdWrInValidAddrRange_13 value="0x00000000" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_14.IASecureRdWrInValidAddrRange_14 value="0x00000000" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IASecureRdWrInValidAddrRange_15.IASecureRdWrInValidAddrRange_15 value="0x00000000" help_text="Secure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Secure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for a secure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_0.IAInSecureRdWrInValidAddrRange_0 value="0x4E924E92" help_text="Note that there are 32 of these such registers, IAInsecureRdWrInvalidAddrRange[32:0]. Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_1.IAInSecureRdWrInValidAddrRange_1 value="0x4FCB4FB5" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_2.IAInSecureRdWrInValidAddrRange_2 value="0x5E185E16" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_3.IAInSecureRdWrInValidAddrRange_3 value="0x5E235E22" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_4.IAInSecureRdWrInValidAddrRange_4 value="0x5E305E30" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_5.IAInSecureRdWrInValidAddrRange_5 value="0x5E615E3C" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_6.IAInSecureRdWrInValidAddrRange_6 value="0x5E6B5E66" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_7.IAInSecureRdWrInValidAddrRange_7 value="0x5FAD5FAC" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_8.IAInSecureRdWrInValidAddrRange_8 value="0x6F356F00" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_9.IAInSecureRdWrInValidAddrRange_9 value="0x6FDB6FD0" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_10.IAInSecureRdWrInValidAddrRange_10 value="0x6FE36FDD" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_11.IAInSecureRdWrInValidAddrRange_11 value="0x1A0A1A07" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_12.IAInSecureRdWrInValidAddrRange_12 value="0x120A1207" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_13.IAInSecureRdWrInValidAddrRange_13 value="0x140A1407" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_14.IAInSecureRdWrInValidAddrRange_14 value="0x1C361C35" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_15.IAInSecureRdWrInValidAddrRange_15 value="0x00000000" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_16.IAInSecureRdWrInValidAddrRange_16 value="0x00000000" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <IAInsecureRdWrInValidAddrRange_17.IAInSecureRdWrInValidAddrRange_17 value="0x00000000" help_text="Insecure PMIC Black list Registers for HOST. List of register ranges in PMIC which are subject to write access control. Host does NOT have access to these registers when Insecure. PMIC addressing utilizes 2 bytes: MSB (byte 1) is base address; LSB (byte 0) is the offset. The range is from bits[15:0] to bits [31:16]. For example, value 0x56781234 would indicate PMIC base address 0x12, offset 0x34 to PMIC base address 0x56, offset 0x78 are inaccessible for an insecure HOST.. " /> + <InsecureWrRegBitMskAddr_0.InsecureWrRegBitMskAddr_0 value="0x03034FD3" help_text="Note that there are 16 of these such registers, InsecureWrRegBitMskAddr[15:0]. Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_1.InsecureWrRegBitMskAddr_1 value="0xFFFD5E24" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_2.InsecureWrRegBitMskAddr_2 value="0x00000000" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_3.InsecureWrRegBitMskAddr_3 value="0x00000000" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_4.InsecureWrRegBitMskAddr_4 value="0x00000000" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_5.InsecureWrRegBitMskAddr_5 value="0x00000000" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_6.InsecureWrRegBitMskAddr_6 value="0x00000000" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <InsecureWrRegBitMskAddr_7.InsecureWrRegBitMskAddr_7 value="0x00000000" help_text="Information for bitwise set or clear permissions for the insecure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_0.SecureWrRegBitMskAddr_0 value="0x03034FD3" help_text="Note that there are 16 of these such registers, SecureWrRegBitMskAddr[15:0]. Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_1.SecureWrRegBitMskAddr_1 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_2.SecureWrRegBitMskAddr_2 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_3.SecureWrRegBitMskAddr_3 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_4.SecureWrRegBitMskAddr_4 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_5.SecureWrRegBitMskAddr_5 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_6.SecureWrRegBitMskAddr_6 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + <SecureWrRegBitMskAddr_7.SecureWrRegBitMskAddr_7 value="0x00000000" help_text="Information for bitwise set or clear permissions for the secure blacklist registers. The data contains the register address (bits[15:8],[7:0] are the device and offset), mask of bits which cannot be SET on a write (bits[23:16]) and mask of bits which cannot be CLEARED on a write (bits[31:24).. " /> + </WHISKEYCOVE_CATEGORY> + <GPIOStraps label="GPIO Straps"> + <PMU_PLTRST_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_PLTRST_B" /> + <PMU_PWRBTN_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_PWRBTN_B" /> + <PMU_SLP_S0_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_SLP_S0_B" /> + <PMU_SLP_S3_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_SLP_S3_B" /> + <PMU_SLP_S4_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_SLP_S4_B" /> + <SUSPWRDNACK value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for SUSPWRDNACK" /> + <EMMC_DNX_PWR_EN_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for EMMC_DNX_PWR_EN_B" /> + <GPIO_105 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_105" /> + <PMU_BATLOW_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_BATLOW_B" /> + <RESETBUTTON value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for RESETBUTTON" /> + <PMU_SUSCLK value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PMU_SUSCLK" /> + <SUS_STAT_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for SUS_STAT_B" /> + <LPSS_I2C5_SDA value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPSS_I2C5_SDA" /> + <LPSS_I2C5_SCL value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPSS_I2C5_SCL" /> + <LPSS_I2C6_SDA value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPSS_I2C6_SDA" /> + <LPSS_I2C6_SCL value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPSS_I2C6_SCL" /> + <LPSS_I2C7_SDA value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPSS_I2C7_SDA" /> + <LPSS_I2C7_SCL value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPSS_I2C7_SCL" /> + <PCIE_WAKE0_B value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_WAKE0_B" /> + <PCIE_WAKE1_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_WAKE1_B" /> + <PCIE_WAKE2_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_WAKE2_B" /> + <PCIE_WAKE3_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_WAKE3_B" /> + <PCIE_CLKREQ0_B value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_CLKREQ0_B" /> + <PCIE_CLKREQ1_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_CLKREQ1_B" /> + <PCIE_CLKREQ2_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_CLKREQ2_B" /> + <PCIE_CLKREQ3_B value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PCIE_CLKREQ3_B" /> + <HV_DDI0_DDC_SDA value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_DDI0_DDC_SDA" /> + <HV_DDI0_DDC_SCL value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_DDI0_DDC_SCL" /> + <HV_DDI1_DDC_SDA value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_DDI1_DDC_SDA" /> + <HV_DDI1_DDC_SCL value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_DDI1_DDC_SCL" /> + <PANEL0_VDDEN value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PANEL0_VDDEN" /> + <PANEL0_BKLTEN value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PANEL0_BKLTEN" /> + <PANEL0_BKLTCTL value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for PANEL0_BKLTCTL" /> + <HV_DDI0_HPD value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_DDI0_HPD" /> + <HV_DDI1_HPD value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_DDI1_HPD" /> + <HV_EDP_HPD value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for HV_EDP_HPD" /> + <GPIO_134 value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_134" /> + <GPIO_135 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_135" /> + <GPIO_136 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_136" /> + <GPIO_137 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_137" /> + <GPIO_138 value="1.8V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_138" /> + <GPIO_139 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_139" /> + <GPIO_140 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_140" /> + <GPIO_141 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_141" /> + <GPIO_142 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_142" /> + <GPIO_143 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_143" /> + <GPIO_144 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_144" /> + <GPIO_145 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_145" /> + <GPIO_146 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for GPIO_146" /> + <LPC_ILB_SERIRQ value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_ILB_SERIRQ" /> + <LPC_CLKOUT0 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_CLKOUT0" /> + <LPC_CLKOUT1 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_CLKOUT1" /> + <LPC_AD0 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_AD0" /> + <LPC_AD1 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_AD1" /> + <LPC_AD2 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_AD2" /> + <LPC_AD3 value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_AD3" /> + <LPC_CLKRUNB value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_CLKRUNB" /> + <LPC_FRAMEB value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for LPC_FRAMEB" /> + </GPIOStraps> + <GPIOSccFuseStraps label="GPIO SCC Fuse Straps"> + <SMB_ALERTB value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for SMB_ALERTB" /> + <SMB_CLK value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for SMB_CLK" /> + <SMB_DATA value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for SMB_DATA" /> + <SDCARD_LVL_WP value="3.3V" value_list="3.3V,,1.8V" help_text="PAD VCCIO select for SDCARD_LVL_WP" /> + </GPIOSccFuseStraps> + </PlatformConfiguration> + <IntelTxeKernel label="Intel(R) TXE Kernel"> + <Processor> + <ProcEmulation value="No Emulation" value_list="No Emulation,,EMULATE Intel (R) vPro (TM) capable Processor,,EMULATE Intel (R) Core (TM) branded Processor,,EMULATE Intel (R) Celeron (R) branded Processor,,EMULATE Intel (R) Pentium (R) branded Processor,,EMULATE Intel (R) Xeon (R) branded Processor,,EMULATE Intel (R) Xeon (R) Manageability capable Processor" label="Processor Emulation" /> + </Processor> + <IntelServicesConfiguration label="Intel(R) Services Configuration"> + <OdmIDIntelServices value="0x00000000" label="ODM ID used by Intel(R) Services" help_text="This setting is for entering the ODM ID for Intel(R) Services to identify the ODM Board builder. Note: This ID is either generated by or registered with Intel(R ) Services Web servers." /> + <SysIntIdIntelServices value="0x00000000" label="System Integrator ID used by Intel(R) Services" help_text="This setting is for entering the System Integrator ID for Intel(R) Services to identify the System Integrator. Note: This ID is either generated by or registered with Intel(R ) Services Web servers." /> + <ReservedIdIntelServices value="0x00000000" label="Reserved ID used by Intel(R) Services" help_text="This setting is for entering the Reserved ID for Intel(R) Services currently not used." /> + </IntelServicesConfiguration> + <ImageIdentification label="Image Identification"> + <OemTag value="0x00000000" label="OEM Tag" /> + </ImageIdentification> + <FirmwareDiagnostics label="Firmware Diagnostics"> + <FwAutoBist value="Disabled" value_list="Disabled,,Enabled" label="Automatic Built in Self Test" help_text="This setting enables the firmware Automatic Built in Self Test which is executed during first platform boot after initial image flashing." /> + </FirmwareDiagnostics> + <ManufacturingSettings label="Manufacturing Settings"> + <EndOfManufacturing value="No" value_list="No,,Yes" label="End of Manufacturing Enable" help_text="EOM should be set when the image is built in production mode. This will trigger close manuf flows in FW. This setting is not configurable in SPI mode." /> + <PostManufLockEnable value="No" value_list="No,,Yes" label="Post Manufacturing NVAR Configuration Enabled" help_text="This setting determines if modifications to Customer configuable NVARs is to be allowed after close of manufacturing." /> + </ManufacturingSettings> + </IntelTxeKernel> + <IsolatedMemoryRanges label="Isolated Memory Ranges"> + <MemoryRanges label="Memory Ranges"> + <Imr00 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr01 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr02 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr03 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr04 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr05 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr06 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr07 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr08 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr09 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr10 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr11 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr12 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr13 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr14 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr15 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr16 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr17 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr18 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + <Imr19 value="0" help_text="Override IMR size setting. Set to 0 to use default configuration value." /> + </MemoryRanges> + </IsolatedMemoryRanges> + <PlatformProtection label="Platform Protection"> + <ContentProtection label="Content Protection"> + <PavpSupported value="Yes" value_list="No,,Yes" label="PAVP Supported" help_text="This setting determines if the Protected Audio Video Path (PAVP) feature will be permanently disabled in the FW image." /> + <CEKBinary value="" label="Content Encryption Key" help_text="This option is for entering the raw hash 256 bit string or certificate file for the Content Encryption" /> + <Lspcon4kdisp value="None" value_list="None,,PortB,,PortC,,PortD" label="LSPCON Internal Display Port 1 - LSPCON / 4K" help_text="This setting determines which port for LSPCON will be connected to the HDCP 2.2 bridge adapter Display 1." /> + <Hdcp5kedisp1 value="PortA" value_list="None,,PortA,,PortB,,PortC,,PortD" label="HDCP Internal Display Port 1 - 5K" help_text="This setting determines which port is connected for 5K output on Internal Display 1. Note: Both Display 1 & 2 need to be configured for proper operation." /> + <Hdcp5kedisp2 value="None" value_list="None,,PortA,,PortB,,PortC,,PortD" label="HDCP Internal Display Port 2 - 5K" help_text="This setting determines which port is connected for 5K output on Internal Display 2. Note: Both Display 1 & 2 need to be configured for proper operation." /> + <VgaPort value="None" value_list="None,,PortA" label="VGA Display Port" help_text="This setting determines if VGA adaptor is configured for port A." /> + </ContentProtection> + <PlatformIntegrity label="Platform Integrity"> + <SmipSigningKey value="@signing_key@" label="SMIP Signing Key" help_text="This is the path to the private key used to sign the SMIP, while public key hash of it is included in the OEM hash manifest. This setting is only configurable when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)."/> + <OemPublicKeyHash value="@key_hash@" label="OEM Public Key Hash" help_text="Raw hash string for the SHA-256 hash of the OEM public key corresponding to the private key used to sign the OEM Key hash manifest. When manufacture is completed, this hash value is burned into an FPF, and is permament. This value is used to verify the OEM Key hash, and also DnX images. OEM signing is disabled when this hash is set to all 0s."/> + <OemExtInputFile value="$SourceDir/build/oemkeymn2.bin" label="OEM Key Manifest Binary" help_text="Signed manifest file containing hashes of keys used for signing components of image. This setting is only configurable when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)."/> + </PlatformIntegrity> + <BootGuardConfiguration label="Boot Guard Configuration"> + <BtGuardKeyManifestId value="0x1" label="Key Manifest ID" help_text="ODM identifier used during the Key manifest authentication process. This setting is only configurable, and must be non-0, when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)." /> + <BtGuardProfileConfig value="Boot Guard Profile 2 - VM" value_list="Boot Guard Profile 0 - Legacy,,Boot Guard Profile 1 - V,,Boot Guard Profile 2 - VM" label="Boot Profile" help_text="Boot Guard Profile 0 - Legacy is for platforms that do not wish to enable Boot Guard boot block verification or measurement protection. Boot Guard Profile 1 - V is Strict Verification Enforcement. Prevents unverified bios components from running. Boot Guard Profile 2 - VM is Strict Verification and Measurement enforcement. Prevents unverified Bios components from running. When manufacture is completed, this value is burned into an FPF, and is permament. This setting is only configurable when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)." /> + <BtGuardS3Optimize value="Enabled" value_list="Enabled,,Disabled" label="S3 Optimization" /> + <BtGuardArbUCode value="No" value_list="No,,Yes" label="uCode Anti Rollback Enable" /> + <BtGuardArbOemKeyManifest value="No" value_list="No,,Yes" label="OEM Key Manifest Anti Rollback Enable" /> + <BtGuardArbBiosMetadata value="No" value_list="No,,Yes" label="Bios Metadata Anti Rollback Enable" /> + <BtGuardArbAndroidOs value="No" value_list="No,,Yes" label="Android OS Anti Rollback Enable" /> + <BtGuardArbIUnitFw value="No" value_list="No,,Yes" label="IUnit Anti Rollback Enable" /> + <BtGuardArbADspFw value="No" value_list="No,,Yes" label="aDSP Anti Rollback Enable" /> + <BtGuardArbIfwi value="No" value_list="No,,Yes" label="IFWI Anti Rollback Enable" /> + <BtGuardArbPmc value="No" value_list="No,,Yes" label="PMC Anti Rollback Enable" /> + </BootGuardConfiguration> + <IntelPttConfiguration label="Intel(R) PTT Configuration"> + <PttPwrUpState value="Enabled" value_list="Disabled,,Enabled" label="Intel(R) PTT initial power-up state" /> + <PttSupported value="Yes" value_list="No,,Yes" label="Intel(R) PTT Supported" /> + <PttSupportedHw value="Yes" value_list="No,,Yes" label="Intel(R) PTT Supported [FPF]" help_text="Permenently Enable/Disable PTT FPF" /> + <PttProfile value="PC-Client" value_list="PC-Client,,Automotive-Thin" label="Intel(R) PTT Profile" /> + </IntelPttConfiguration> + <IntelFpfAntiRollbackConfiguration label="Intel FPF Anti-Rollback Configuration"> + <CseArbEnabled value="No" value_list="No,,Yes" label="CSE Manifest Anti-Rollback Enabled" help_text="This setting enables Anti-Roll back for the CSE Engine binary." /> + <OemKmArbEnabled value="No" value_list="No,,Yes" label="OEM Key Manifest Anti-Rollback Enabled" help_text="This setting enables Anti-Roll back for the OEM Key Manifest Engine binary." /> + <UcodeArbEnabled value="No" value_list="No,,Yes" label="uCode Manifest Anti-Rollback Enabled" help_text="This setting enables Anti-Roll back for the uCode Engine binary." /> + </IntelFpfAntiRollbackConfiguration> + <TpmOverSpiBusConfiguration label="TPM Over SPI Bus Configuration"> + <DiscreteTpmLocation value="SPI" value_list="None,,LPC,,SPI" label="Discrete TPM Location" help_text="Location of discrete TPM" /> + <SpiOverTpmClkFreq value="17MHz" value_list="17MHz,,30MHz,,48MHz,,60MHz,,120MHz" label="TPM Clock Frequency" help_text="This field identifies the serial clock frequency for TPM on SPI. This field is undefined if the TPM on SPI is disabled either by softstrap or fuse. This field is defined with a broad range to support SOC implementations. The listed frequencies are approximate." /> + </TpmOverSpiBusConfiguration> + <DalAppletSigning label="DAL Applet Signing"> + <OemSigningDalApplet value="No" value_list="No,,Yes" label="Allow OEM Signing of DAL Applets" help_text="FPF that enables OEM signing of DAL applets." /> + </DalAppletSigning> + </PlatformProtection> + <IntegratedSensorHub label="Integrated Sensor Hub"> + <IshSupported value="No" value_list="No,,Yes" label="Integrated Sensor Hub Supported" help_text="This setting allows customers to permanently disable ISH FPF on the platform." /> + <IshPowerUpState value="Disabled" value_list="Disabled,,Enabled" label="Integrated Sensor Hub Initial Power State" help_text="This setting allows customers to determine the power up state for ISH." /> + <IshImage label="ISH Image"> + <Length value="0x40000" help_text="Total size (in bytes) of the ISH code partition including reserved space. It is recommended to be at least 256kb." /> + <InputFile value="" label="Input File" help_text="Path to your ISH firmware binary file." /> + </IshImage> + <IshData label="ISH Data"> + <PdtBinary value="@bom3@" label="PDT Binary File" help_text="Path to your PDT binary file."/> + </IshData> + </IntegratedSensorHub> + <IUnit label="iUnit"> + <IUnitSecureTouch label="Secure Touch"> + <IUnitSecureTouch value="Disabled" value_list="Disabled,,Enabled" label="Secure Touch" help_text="If enabled, the CSI streams identified by the CAMERA_MASK register have all pixels replaced by a fixed value (i.e. disable camera)" /> + </IUnitSecureTouch> + <IUnitSecurityControl label="Security Control"> + <IUnitFWSecureMode value="Enabled" value_list="Disabled,,Enabled" label="Firmware Secure Mode" help_text="If enabled, access blockers in IS and PS are enabled, so as to authenticate camera firmware. Must be enabled for FW authentication flow and execution of authenticated FW." /> + <IUnitDfxSecFeatEnOvrd value="Enabled" value_list="Disabled,,Enabled" label="Dfx Secure Feature En Override" help_text="If enabled, NPK is enabled, else dfxsecure_feature_en signal is checked to see if the NPK feature should be enabled or not." /> + </IUnitSecurityControl> + <IUnitCameraMask label="Camera Mask"> + <IUnitCameraMask1 value="0x0000003F" label="Camera Mask 1" help_text="Bit mask that identifies cameras that are subject to secure touch, in CSI port A. 1 indicates camera is subject to secure touch, 0 means it is not." /> + <IUnitCameraMask2 value="0x0000003F" label="Camera Mask 2" help_text="Bit mask that identifies cameras that are subject to secure touch, in CSI port B. 1 indicates camera is subject to secure touch, 0 means it is not." /> + </IUnitCameraMask> + <IUnitCSI2PortConfigAB label="CSI2 Port Config AB"> + <IUnitPortIdA value="0x10" label="PORT_ID_A" help_text="Specifies configuration of cameras and data lanes allocated to each camera port, for CSI port A. (MSB not used). The 20-pins of set A can be configured and connected to up to four cameras in the platform using MIPI DPHY protocol. The field PORT_ID_A is used to select the number of cameras (also called ports) and the number of data lanes allocated to each camera port. See IUNIT AE for more information on how to configure this field." /> + <IUnitPortIdB value="0x10" label="PORT_ID_B" help_text="Specifies configuration of cameras and data lanes allocated to each camera port, for CSI port B. (MSB not used). The 12-pins of set B can be configured and connected to either four cameras in the platform using MIPI CPHY protocol OR up to two cameras in the platform using the MIPI DPHY protocol. See IUNIT AE for more information on how to configure this field." /> + </IUnitCSI2PortConfigAB> + </IUnit> + <Debug> + <Idlm label="IDLM"> + <IdlmBinary value="" label="IDLM Binary" help_text="This allows an IDLM binary to be merged into output image built by Intel (R) FIT" /> + </Idlm> + <IntelTraceHubTechnology label="Intel(R) Trace Hub Technology"> + <IntelTrcHubBinary value="" label="Intel(R) Trace Hub Binary" help_text="This loads the Intel (R) Trace Hub binary that will be merged into the into the output image generated by the Intel(R) FIT tool." /> + <UtokLength value="0x2000" /> + <UnlockToken value="" label="Unlock Token" help_text="This allows the OEM to input an Unlock Token binary file for closed chassis debug." /> + <NpkPtiDis value="Enabled" value_list="Enabled,,Disabled" label="Early boot NPK" help_text="This configuration allows enabling/disabling NorthPeak logging capability for early boot. By enabling this feature, TXE engine will control GPIO_0 to GPIO_4 pins for PTI. Disable it if you do not wish for TXE to control these GPIOs" /> + </IntelTraceHubTechnology> + <IntelTxeFirmwareDebuggingOverrides label="Intel(R) TXE Firmware Debugging Overrides"> + <DbgOverridePreProdSi value="0x00000000" label="Debug Override Pre-Production Silicon" help_text="Allows the OEM to control FW features to assist with pre-production platform debugging. This control has no effect if used on production silicon. Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." /> + <DbgOverrideProdSi value="0x00000000" label="Debug Override Production Silicon" help_text="Allows the OEM to control FW features to assist with production platform debugging. Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." /> + <TxeRomBypassEnable value="No" value_list="No,,Yes" label="Firmware ROM Bypass" /> + </IntelTxeFirmwareDebuggingOverrides> + <HvmFuseEmulation label="HVM Fuse Emulation"> + <EmulateOverrideSocDevReuseDisabled value="No" value_list="No,,Yes" label="Override SoC Device Reuse HVM fuse value Emulation" help_text="See SPI and SMIP Programming Guide for more information" /> + </HvmFuseEmulation> + </Debug> + <Dnx label="Download and Execute"> + <DnxConfiguration label="DnX Configuration"> + <DnxEnabled value="Yes" value_list="Yes,,No" label="DnX Enabled" help_text="DnX permanent enable/disable FPF" /> + <DnxPlatformId value="0x0" label="Platform ID" help_text="Platform ID that DnX uses to verify the image is suitable for the platform. Before FPFs lock, this field is ignored and DnX will accept any image. After FPS lock, only images with this Platform ID will be accepted by DnX." /> + <DnxOemId value="0x0" label="OEM ID" help_text="OEM ID that DnX uses to verify the image is suitable for the platform. Before FPFs lock, this field is ignored and DnX will accept any image. After FPF lock, only images with this OEM ID will be accepted by DnX." /> + <DnxLedEnabled value="No" value_list="Yes,,No" label="LED Enabled" help_text="DnX LED Permanently Enabled/Disabled FPF" /> + <BuildEnabled value="No" value_list="No,,Yes" help_text="Should Intel FIT build a DnX image" /> + <OutputFileName value="$WorkingDir\dnx.bin" /> + <SigningKey value="" help_text="The path to the private key to use to sign the DnX image. This setting is only configurable when OEM signing is enabled (See PlatformIntegrity/OemPublicKeyHash)." /> + </DnxConfiguration> + <UsbDnxDescriptor label="USB Descriptor"> + <DnxUsbStringDescriptor1 value="" label="USB String Descriptor 1" help_text="Used by ROM to communicate manufacturer string (32 characters) to recovery host. If this descriptor is not defined by OEM, identified by all 0’s, ROM will use default descriptors" /> + <DnxUsbStringDescriptor2 value="" label="USB String Descriptor 2" help_text="Used by ROM to communicate manufacturer string (32 characters) to recovery host. If this descriptor is not defined by OEM, identified by all 0’s, ROM will use default descriptors" /> + </UsbDnxDescriptor> + <DnxSpiConfiguration label="DnX SPI Regions Configuration"> + <DnxSpiIfwiRegion value="Yes" value_list="No,,Yes" label="Enable DnX SPI Region IFWI" help_text="Enable DnX SPI flash update of IFWI region." /> + <DnxSpiPdrRegion value="Yes" value_list="No,,Yes" label="Enable DnX SPI Region PDR" help_text="Enable DnX SPI flash update of PDR region." /> + </DnxSpiConfiguration> + </Dnx> + <EspiConfig label="eSPI Configuration"> + <SpiEcBootDis value="No" value_list="No,,Yes" label="EC Boot Load - For Slave 0 (EC/BMC) disabled" help_text="EC_BOOT_LOAD_DONE is internally forced asserted immediately" /> + <SpiEcCrcchkDis value="No" value_list="No,,Yes" label="CRC Check for EC - For Slave 0 disabled" /> + <espi_freq_divby8_ovrd value="No" value_list="Yes,,No" label="eSPI bus low frequency" help_text="eSPI bus low frequency (div-by-8) mode" /> + </EspiConfig> +</FitData> -- To view, visit https://review.coreboot.org/c/coreboot/+/59366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I840ae803fe9fc83a0d1aeb48adf757e096ac5639 Gerrit-Change-Number: 59366 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpu.c: Remove unused variables
by Angel Pons (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Arthur Heymans, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Patrick Rudolph, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58602 ) Change subject: soc/intel/xeon_sp/cpu.c: Remove unused variables ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/58602/comment/be488f19_0e7f2f95 PS1, Line 204: intel_update_microcode_from_cbfs > > This has an extra spinlock, does it matter? […] Would be good to test, just in case. Also, please mention this functional difference in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/58602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id809cd78fb9da98b9514fcf8d8057dccf2987d23 Gerrit-Change-Number: 58602 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 22:03:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/romstage: Preload fspm.bin
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58988 to look at the new patch set (#7). Change subject: soc/amd/cezanne/romstage: Preload fspm.bin ...................................................................... soc/amd/cezanne/romstage: Preload fspm.bin FSP-M is normally memmapped and then decompressed. The SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time | 970 - loading FSP-M | 0.31 | 0.992 Δ( 0.68, 0.04%) | | 15 - starting LZMA decompress (ignore for x86) | 0.024 | 9.472 Δ( 9.45, 0.62%) | | 16 - finished LZMA decompress (ignore for x86) | 54.011 | 11.05 Δ(-42.96, -2.82%) | Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I850b1576501753a355e7b23745e04802a0560387 --- M src/soc/amd/cezanne/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/58988/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850b1576501753a355e7b23745e04802a0560387 Gerrit-Change-Number: 58988 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 3: (2 comments) File src/include/mutex.h: PS2: > License Done https://review.coreboot.org/c/coreboot/+/59320/comment/9807d471_40f9f83d PS2, Line 11: void mutex_unlock(struct mutex *mutex); > These should be static inline no-ops when neither SMP nor threading is enabled. So I wanted to make it so the lock/unlock asserts were checked regardless of threading or SMP. This way we don't introduce code that works with coop disabled, but then breaks when coop is enabled. I felt the increase in BSS and code was small enough that it was worth it. What do you think? Otherwise I can add a check into the functions: i.e., ``` if (ENV_STAGE_SUPPORTS_SMP) mutex_lock_smp(mutex); else if (CONFIG(COOP_MULTITASKING)) mutex_lock_nosmp(mutex); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 21:54:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian. Hello build bot (Jenkins), Julius Werner, Rob Barnes, Kyösti Mälkki, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59320 to look at the new patch set (#3). Change subject: lib: Add a mutex ...................................................................... lib: Add a mutex We currently have two synchronization primatives, spinlock and thread_mutex. spinlock is meant to block multiple CPUs from entering a critical section. thread_mutex is meant to block multiple coop-threads from entering a critical section. It is not AP aware at all. This CL introduces a mutex that can handle both concepts. The implementation is using the GCC/LLVM atomic builtin functions. The generated code uses the xchg instruction vs spinlock which uses (lock) decb. 8: b0 01 mov $0x1,%al a: 86 03 xchg %al,(%ebx) c: 84 c0 test %al,%al BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 --- A src/include/mutex.h M src/lib/Makefile.inc A src/lib/mutex.c 3 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/59320/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS
by Raul Rangel (Code Review) 16 Nov '21

16 Nov '21

Raul Rangel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59021 ) Change subject: arch/x86/smp/spinlock: Fix threading when !STAGE_HAS_SPINLOCKS ...................................................................... Abandoned Replaced with this patch train: https://review.coreboot.org/c/coreboot/+/59320 -- To view, visit https://review.coreboot.org/c/coreboot/+/59021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea621fcdad8f0367acce4f70be42a4e9a68da938 Gerrit-Change-Number: 59021 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: abandon

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coreboot-gerrit November 2021