coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58373 ) Change subject: mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz ...................................................................... mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz Update board type to 4 as per MRC team's input. This fixes LP5 sagv point 3 being clipped from the expected 5200Mhz to 4800Mhz. TEST=Boot to OS, verify frequency locked. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/adlrvp/memory.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Selma Bensaid: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 93f1aa3a2..f4ae541 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -227,7 +227,7 @@ .LpDdrDqDqsReTraining = 1, - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, }; static const struct mb_cfg adlm_lp5_mem_config = { @@ -283,7 +283,7 @@ .ect = false, /* Early Command Training */ - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, .lp5x_config = { .ccc_config = 0xff, -- To view, visit https://review.coreboot.org/c/coreboot/+/58373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99 Gerrit-Change-Number: 58373 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/mb/google: Change comments in memory Makefile.inc templates
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59297 ) Change subject: util/mb/google: Change comments in memory Makefile.inc templates ...................................................................... util/mb/google: Change comments in memory Makefile.inc templates Begin comments with # instead of ## to match the Makefile.inc generated by spd_tools. BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman(a)google.com> Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59297 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M util/mainboard/google/brya0/template/memory/Makefile.inc M util/mainboard/google/dalboz/template/spd/Makefile.inc M util/mainboard/google/guybrush/template/memory/Makefile.inc M util/mainboard/google/trembyle/template/spd/Makefile.inc M util/mainboard/google/volteer/template/memory/Makefile.inc M util/mainboard/google/waddledee/template/memory/Makefile.inc M util/mainboard/google/waddledoo/template/memory/Makefile.inc 7 files changed, 21 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/util/mainboard/google/brya0/template/memory/Makefile.inc b/util/mainboard/google/brya0/template/memory/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/brya0/template/memory/Makefile.inc +++ b/util/mainboard/google/brya0/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/dalboz/template/spd/Makefile.inc b/util/mainboard/google/dalboz/template/spd/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/dalboz/template/spd/Makefile.inc +++ b/util/mainboard/google/dalboz/template/spd/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/guybrush/template/memory/Makefile.inc b/util/mainboard/google/guybrush/template/memory/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/guybrush/template/memory/Makefile.inc +++ b/util/mainboard/google/guybrush/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/trembyle/template/spd/Makefile.inc b/util/mainboard/google/trembyle/template/spd/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/trembyle/template/spd/Makefile.inc +++ b/util/mainboard/google/trembyle/template/spd/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/volteer/template/memory/Makefile.inc b/util/mainboard/google/volteer/template/memory/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/volteer/template/memory/Makefile.inc +++ b/util/mainboard/google/volteer/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/waddledee/template/memory/Makefile.inc b/util/mainboard/google/waddledee/template/memory/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/waddledee/template/memory/Makefile.inc +++ b/util/mainboard/google/waddledee/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/waddledoo/template/memory/Makefile.inc b/util/mainboard/google/waddledoo/template/memory/Makefile.inc index 6751a42..eace2e4 100644 --- a/util/mainboard/google/waddledoo/template/memory/Makefile.inc +++ b/util/mainboard/google/waddledoo/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder -- To view, visit https://review.coreboot.org/c/coreboot/+/59297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e Gerrit-Change-Number: 59297 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Fix S0ix regression
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58178 ) Change subject: mb/intel/adlrvp: Fix S0ix regression ...................................................................... mb/intel/adlrvp: Fix S0ix regression The following changes are needed to fix S0ix regression on RVP 1) Disable Clk src 3 2) Disable Ext FIVR settings TEST=Boot adlrvp to OS, confirm S0ix is working. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 0 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a00ad35..8926887 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,12 +83,6 @@ .clk_src = 0, }" - # Enable CPU PCIE RP 2 using CLK 3 - register "cpu_pcie_rp[CPU_RP(2)]" = "{ - .clk_req = 3, - .clk_src = 3, - }" - # Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_req = 4, @@ -187,21 +181,6 @@ }, }" - # FIVR configurations - register "ext_fivr_settings" = "{ - .configure_ext_fivr = 1, - .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, - .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .v1p05_voltage_mv = 1050, - .vnn_voltage_mv = 1050, - .vnn_sx_voltage_mv = 1050, - .v1p05_icc_max_ma = 500, - .vnn_icc_max_ma = 500, - }" - device domain 0 on device ref pcie5 on end device ref igpu on end -- To view, visit https://review.coreboot.org/c/coreboot/+/58178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882 Gerrit-Change-Number: 58178 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Archana Patni <archana.patni(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Sonam Sanju <sonam.sanju(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/primus: enable ALC5682I-VS
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59173 ) Change subject: mb/google/brya/variants/primus: enable ALC5682I-VS ...................................................................... mb/google/brya/variants/primus: enable ALC5682I-VS In next phase build, the audio codec will change to ALC5682I-VS BUG=b:205883511 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com> Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus/variant.c 2 files changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 8028798..48319b7 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -182,7 +182,7 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on + device i2c 1a alias audio_codec on probe AUDIO MAX98360_ALC5682I_I2S end end diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c index 4780334..b783ac0 100644 --- a/src/mainboard/google/brya/variants/primus/variant.c +++ b/src/mainboard/google/brya/variants/primus/variant.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <boardid.h> #include <device/device.h> +#include <drivers/i2c/hid/chip.h> static void devtree_update_emmc_rtd3(uint32_t board_ver) { @@ -13,8 +14,21 @@ emmc_rtd3->enabled = 0; } +static void devtree_update_audio_codec(uint32_t board_ver) +{ + struct device *audio_codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config = audio_codec->chip_info; + + if (board_ver <= 1) + return; + + config->hid = "RTL5682"; + audio_codec->enabled = 1; +} + void variant_devtree_update(void) { uint32_t board_ver = board_id(); devtree_update_emmc_rtd3(board_ver); + devtree_update_audio_codec(board_ver); } 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95 Gerrit-Change-Number: 59173 Gerrit-PatchSet: 12 Gerrit-Owner: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Set flag comboable as bool type
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Bao Zheng, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59093 ) Change subject: amdfwtool: Set flag comboable as bool type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de Gerrit-Change-Number: 59093 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 17 Nov 2021 00:31:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add a union for combo and psp directory
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Bao Zheng, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58557 ) Change subject: amdfwtool: Add a union for combo and psp directory ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9 Gerrit-Change-Number: 58557 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 17 Nov 2021 00:30:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add NVRAM counter for TPM 2.0
by Andrey Pronin (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Miriam Polzer, Yu-Ping Wu. Andrey Pronin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59097 ) Change subject: security/vboot: Add NVRAM counter for TPM 2.0 ...................................................................... Patch Set 6: (2 comments) File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/59097/comment/9860b778_48281ba2 PS6, Line 120: TPMA_NV_WRITE_STCLEAR do we need the ability to WriteLock until reboot? https://review.coreboot.org/c/coreboot/+/59097/comment/43bf9498_e0a10335 PS6, Line 385: enterprise_rollback_create_counter adding it here only creates the counter on new devices, which didn't pass factory_initialize yet (happens on the first boot with coreboot normally). is it what's expected? -- To view, visit https://review.coreboot.org/c/coreboot/+/59097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1 Gerrit-Change-Number: 59097 Gerrit-PatchSet: 6 Gerrit-Owner: Miriam Polzer <mpolzer(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Miriam Polzer <mpolzer(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 00:17:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS A/B recovery feature
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56773 ) Change subject: amdfwtool: Add support for AMD's BIOS A/B recovery feature ...................................................................... Patch Set 36: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/56773/comment/a1ddcd86_bb8b02f2 PS36, Line 264: { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, : { .type = AMD_ABL1, .level = PSP_BOTH }, : { .type = AMD_ABL2, .level = PSP_BOTH }, : { .type = AMD_ABL3, .level = PSP_BOTH }, : { .type = AMD_ABL4, .level = PSP_BOTH }, : { .type = AMD_ABL5, .level = PSP_BOTH }, : { .type = AMD_ABL6, .level = PSP_BOTH }, : { .type = AMD_ABL7, .level = PSP_BOTH }, from the documentation i'd assume that those should all be the same. not sure that it would make a difference in practice, since the newer socs seem to only use abl0 -- To view, visit https://review.coreboot.org/c/coreboot/+/56773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Gerrit-Change-Number: 56773 Gerrit-PatchSet: 36 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 17 Nov 2021 00:15:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Upgrade "relative address" to four address modes
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59308 ) Change subject: amdfwtool: Upgrade "relative address" to four address modes ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: for mandolin (picasso) this resulted in an identical firmware image in a timeless build, but for guybrush (cezanne) i got a different image when applying this patch compared to just having the previous patch applied. not sure if this is intended or not -- To view, visit https://review.coreboot.org/c/coreboot/+/59308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Gerrit-Change-Number: 59308 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 17 Nov 2021 00:11:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP soc: Added dram information to cbmem WIP
by Julius Werner (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: WIP soc: Added dram information to cbmem WIP ...................................................................... Patch Set 3: (5 comments) File src/soc/qualcomm/common/include/soc/mmu_common.h: https://review.coreboot.org/c/coreboot/+/59195/comment/145a6170_c6c21fff PS3, Line 13: static struct region * const ddr_region = (struct region *)_ddr_information; We don't need ddr_region anymore because mem_chip_info contains the same information (and more). Let's get rid of the ddr_region code and replace it with this while we are adding this. (Please also give us an SC7180 QcLib that supports this then, so we don't break that.) https://review.coreboot.org/c/coreboot/+/59195/comment/be3514ea_af240d9d PS3, Line 14: struct region This isn't a struct region, this is the mem_chip_info struct (which you should define somewhere in some generic header, e.g. <mem_chip_info.h>). File src/soc/qualcomm/common/include/soc/qclib_common.h: https://review.coreboot.org/c/coreboot/+/59195/comment/cb274e8d_ebc11d9b PS3, Line 25: /* memchip info */ This comment adds absolutely nothing useful to this code. File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/59195/comment/d0e53a4c_435dafa5 PS3, Line 27: #if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ Please clean this stuff up so we can properly read the file. File src/soc/qualcomm/sc7280/memlayout.ld: https://review.coreboot.org/c/coreboot/+/59195/comment/8bb1b4b7_490f4e7e PS3, Line 51: REGION(mem_chip_info, 0x1494E000, 1K, 1K) /* memchip info */ I don't really think we need to put this in a separate SRAM region anymore. You can just have the structure allocated as a global variable to pass to QcLib (it's not that big), and then copy it straight into CBMEM afterwards (you can use the platform_romstage_postram() hook for that). -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 00:05:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021