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Change in coreboot[master]: soc/intel/alderlake: Enable CPPCv3 for Intel Alderlake
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

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Change in coreboot[master]: soc/intel/alderlake: Define the helper functions
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59362 ) Change subject: soc/intel/alderlake: Define the helper functions ...................................................................... soc/intel/alderlake: Define the helper functions The patch defines following helper functions: get_cpu_scaling_factor(): Returns scaling factors of big and small core. cpu_is_nominal_freq_supported(): Returns TRUE if cpu supports Nominal Frequency, otherwise FASLE. get_cpu_type(): It returns type of core that is executing the function. TEST=Verified on Brya Signed-off-by: Sridahr Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/59362/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index ab25646..0e13b32 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -278,6 +278,10 @@ /* Fill in Above 4GB MMIO resource */ sa_fill_gnvs(gnvs); + + /* Fill core info */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + core_fill_gnvs(gnvs); } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index be8b011..259374e 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -87,6 +87,17 @@ return CPUID_CORE_TYPE_INTEL_CORE; } +void get_cpu_scaling_factor(uint16_t *big_core_scal_factor, uint16_t *small_core_scal_factor) +{ + *big_core_scal_factor = 1.27; + *small_core_scal_factor = 1; +} + +bool cpu_is_nominal_freq_supported(void) +{ + return TRUE; +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 06b44a2..24428fd 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -33,4 +33,10 @@ /* It returns the cpu type - big or small core */ uint8_t get_cpu_type(void); + +/* Get scaling factors for big and small cores */ +void get_cpu_scaling_factor(uint16_t *big_core_scal_factor, uint16_t *small_core_scale_factor); + +/* Check cpu supports Nominal Frequency or not */ +bool cpu_is_nominal_freq_supported(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963690a4fadad322095d202bcc08c92dcd845360 Gerrit-Change-Number: 59362 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Define a method to return a cpu type
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59361 ) Change subject: soc/intel/alderlake: Define a method to return a cpu type ...................................................................... soc/intel/alderlake: Define a method to return a cpu type The patch implements get_cpu_type() function returns the type of cpu that executing the function. TEST=Verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ifecedac822de71ebbdd43afe8431fd8aa1cdba4c --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/include/soc/cpu.h 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/59361/1 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 59f50f1..be8b011 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -62,6 +62,31 @@ wrmsr(MSR_POWER_CTL, msr); } +static uint32_t cpu_get_family(void) +{ + return cpuid_eax(1) & 0x0FFF0FF0; +} + +uint8_t get_cpu_type(void) +{ + if (cpu_is_hybrid_supported()) { + union cpuid_nat_model_id_and_core_type { + struct { + unsigned int native_mode_id:24; + unsigned int core_type:8; + } bits; + unsigned int hybrid_info; + }; + union cpuid_nat_model_id_and_core_type eax; + + eax.hybrid_info = cpuid_eax(CPUID_HYBRID_INFORMATION); + return (UINT8) eax.bits.core_type & 0xFF; + } else if (cpu_get_family() == CPUID_FULL_FAMILY_MODEL_ALDERLAKE_ATOM) + return CPUID_CORE_TYPE_INTEL_ATOM; + else + return CPUID_CORE_TYPE_INTEL_CORE; +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 233e0c2..06b44a2 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -31,4 +31,6 @@ /* Get a bitmask of supported LPM states */ uint8_t get_supported_lpm_mask(void); +/* It returns the cpu type - big or small core */ +uint8_t get_cpu_type(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifecedac822de71ebbdd43afe8431fd8aa1cdba4c Gerrit-Change-Number: 59361 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel, soc/common: Add method to determine the cpu type mask
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Sridhar Siricilla, Tim Wawrzynczak, Patrick Rudolph. Hello Sridhar Siricilla, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59360 to review the following change. Change subject: soc/intel, soc/common: Add method to determine the cpu type mask ...................................................................... soc/intel, soc/common: Add method to determine the cpu type mask The patch adds below functions: get_cpu_type_bitmask(): It returns the cpu type mask. set_cpu_type_bitmask(): It determines the cpu type (big or small) that is executing the function, and marks the bit location which is corresponds to the executing cpu's index if the cpu type is big. Also, it calls the set_cpu_type_bitmask() from soc/alderlake/cpu.c TEST=verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59360/1 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 94658c7..59f50f1 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -19,6 +19,7 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <intelblocks/acpi.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -87,6 +88,10 @@ /* Enable Turbo */ enable_turbo(); + + /* Set CPU Type bitmask */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + set_cpu_type_bitmask(); } static void per_cpu_smm_trigger(void) diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 83b9c47..4a46433 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -2,9 +2,29 @@ #include <intelblocks/acpi.h> #include <soc/cpu.h> #include <stdlib.h> +#include <cpu/x86/mp.h> +#include <smp/spinlock.h> #define XPPC_PACKAGE_NAME "XCPC" +DECLARE_SPIN_LOCK(cpu_lock); +static unsigned int global_cpu_type_bitmask; + +void set_cpu_type_bitmask(void) +{ + spin_lock(&cpu_lock); + + /* if cpu type is big, mark the bit location corresponds to the cpu index */ + if (get_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE) + global_cpu_type_bitmask |= (1 << get_cpu_index()); + spin_unlock(&cpu_lock); +} + +uint32_t get_cpu_type_bitmask(void) +{ + return global_cpu_type_bitmask; +} + void core_fill_gnvs(struct global_nvs *gnvs) { uint16_t big_core_scal_factor, small_core_scal_factor; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 516c66f..8a5b10e 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -9,6 +9,9 @@ #include <soc/pm.h> #include <stdint.h> +#define CPUID_CORE_TYPE_INTEL_ATOM 0x20 +#define CPUID_CORE_TYPE_INTEL_CORE 0x40 + /* It generates ACPI code to set Nominal Frequency and Nominal Performance */ void acpi_write_xppc_method(int core_id); @@ -116,4 +119,13 @@ /* Fill SSDT for SGX status, EPC base and length */ void sgx_fill_ssdt(void); +/* + * It determins type (big or small) of cpu that is executing the function, and marks + * the bit location which is corresponds to executing cpu's index if the cpu type is big + */ +void set_cpu_type_bitmask(void); + +/* Returns CPU type mask */ +uint32_t get_cpu_type_bitmask(void); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Gerrit-Change-Number: 59360 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core ...................................................................... soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core The patch implements ACPI CPPCv3 package. It implements and updates the following methods: core_fill_gnvs(): It update GNVS hybrid core specific elements generate_cppc_entries(): Updates method to support CPPCv3 package acpigen_write_CPPC_hybrid_method(): It generates ACPI code to implement _CPC method and calls XPPPC method. acpi_write_xppc_method(): It generate ACPI code if cpu supports Nominal Frequency. It generates ACPI code which sets Nominal Frequency and update Nominal Performance. It uses below calculation to update the Nominal Frequency and Nominal Performance: Nominal Frequency = Max non-turbo ratio * cpu_bus_frequency Nominal Performance = Max non-turn ratio * cpu scaling factor Cpu scaling factor varies in the hybrid core environment. So, the generated ACPI code updates Nominal based on the cpu's scaling factor. It also updates GNVS structure. TEST=Verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I12205df9085b51061df5bb7069e6d3ea45535d3d methods to generate ACPI code. Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl A src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/nvs.h 7 files changed, 117 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59359/1 diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 07e9bea..9c21849 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -8,6 +8,9 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO bool +config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + bool + config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT bool depends on HAVE_ACPI_TABLES diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index a6eb80d..0286d94 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -5,3 +5,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) += pep.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) += sgx.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID) += cpu_hybrid.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index b827c58..21d5d1e 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -21,6 +21,7 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <cpu/x86/lapic.h> +#include <stdlib.h> #define CPUID_6_EAX_ISST (1 << 7) @@ -372,19 +373,31 @@ static void generate_cppc_entries(int core_id) { + int version = CPPC_VERSION_2; + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + version = CPPC_VERSION_3; + if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && cpuid_eax(6) & CPUID_6_EAX_ISST)) return; - /* Generate GCPC package in first logical core */ + /* Generate CPPC package & XPPC method in first logical core */ if (core_id == 0) { struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + + cpu_init_cppc_config(&cppc_config, version); acpigen_write_CPPC_package(&cppc_config); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + acpi_write_xppc_method(core_id); } /* Write _CPC entry for each logical core */ - acpigen_write_CPPC_method(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) + acpigen_write_CPPC_hybrid_method(core_id); + else + acpigen_write_CPPC_method(); } __weak void soc_power_states_generation(int core_id, diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index ab63a5c..001ca19 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -25,4 +25,9 @@ A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource , 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code) + SFBC, 16, // 0x48 - 0x49 Indicates Scaling factor for Big core + SFSC, 16, // 0x50 - 0x51 Indicates Scaling Factor for Small Core + NMFQ, 16, // 0x52 - 0x53 Indicates Nominal Frequency + CORE, 32, // 0x54 - 0x57 Each marked bit indicates Big Core corresponding to core index + INFS, 8, // 0x58 - Nominal Frequency is supported } diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c new file mode 100644 index 0000000..83b9c47 --- /dev/null +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -0,0 +1,79 @@ +#include <acpi/acpigen.h> +#include <intelblocks/acpi.h> +#include <soc/cpu.h> +#include <stdlib.h> + +#define XPPC_PACKAGE_NAME "XCPC" + +void core_fill_gnvs(struct global_nvs *gnvs) +{ + uint16_t big_core_scal_factor, small_core_scal_factor; + uint8_t max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); + get_cpu_scaling_factor(&big_core_scal_factor, &small_core_scal_factor); + + /* ADL supports Nominal Frequency */ + gnvs->infs = cpu_is_nominal_freq_supported(); + gnvs->nmfq = max_non_turbo_ratio * cpu_get_bus_frequency(); + gnvs->core = get_cpu_type_bitmask(); + + /* Update big core scaling frequency */ + gnvs->sfbc = (uint16_t)(max_non_turbo_ratio * big_core_scal_factor); + + /* Update small core scaling frequency */ + gnvs->sfsc = (uint16_t)(max_non_turbo_ratio * small_core_scal_factor); +} + +void acpi_write_xppc_method(int core_id) +{ + acpigen_write_method(XPPC_PACKAGE_NAME, 1); + + /* + * If nominal frequency is supported, then set core's nominal performance to + * a scaling factor based on core_id is big or small core. + */ + + acpigen_write_if_lequal_namestr_int("INFS", 1); + acpigen_set_package_element_namestr(CPPC_PACKAGE_NAME, 22, "NMFQ"); + + /* LOCAL2_OP = (CORE >> core_id) & 1 */ + acpigen_emit_byte(SHIFT_RIGHT_OP); + acpigen_emit_namestring("CORE"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP); + + /* + * If core id is big Core, then set big core's scaling factor + * to core's nominal frequency otherwise set small core's scaling factor. + */ + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_set_package_element_namestr(CPPC_PACKAGE_NAME, 3, "SFBC"); + acpigen_write_else(); + acpigen_set_package_element_namestr(CPPC_PACKAGE_NAME, 3, "SFSC"); + acpigen_pop_len(); + acpigen_pop_len(); /* if (INFS == 1) */ + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(CPPC_PACKAGE_NAME); + acpigen_pop_len(); +} + +void acpigen_write_CPPC_hybrid_method(int core_id) +{ + char *pscope; + + if (core_id == 0) { + pscope = (char *) malloc(12); + snprintf(pscope, 12, XPPC_PACKAGE_NAME, 0); + } else { + pscope = (char *) malloc(16); + snprintf(pscope, 16, CONFIG_ACPI_CPU_STRING "." XPPC_PACKAGE_NAME, 0); + } + + acpigen_write_method("_CPC", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(pscope); + acpigen_write_dword(core_id); + acpigen_pop_len(); + free(pscope); +} diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 2d3136e..516c66f 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -9,12 +9,20 @@ #include <soc/pm.h> #include <stdint.h> +/* It generates ACPI code to set Nominal Frequency and Nominal Performance */ +void acpi_write_xppc_method(int core_id); + +/* It generates ACPI code to define _CPC control method */ +void acpigen_write_CPPC_hybrid_method(int core_id); + /* Forward declare the power state struct here */ struct chipset_power_state; /* Forward declare the global nvs structure here */ struct global_nvs; +void core_fill_gnvs(struct global_nvs *gnvs); + /* Return ACPI name for this device */ const char *soc_acpi_name(const struct device *dev); diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 5adbdb8..47522fd 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -27,6 +27,11 @@ u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ u64 hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */ + u16 sfbc; /* Indicates the Scaling Factor for Big Core */ + u16 sfsc; /* Indicates the Scaling Factor for Small Core */ + u16 nmfq; /* Nominal Frequency */ + u32 core; /* Each marked bit indicates a Big Core corresponding to core index */ + u8 infs; /* Indicates if the processor supports nominal frequency */ }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59358 ) Change subject: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition ...................................................................... src/include/acpi: Move CPPC_PACKAGE_NAME macro definition The patch move CPPC_PACKAGE_NAME macro definition from acpi/acpigen.c to include/acpi/acpigen.h. TEST=Verified on Brya. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/59358/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 2b74261..ff04d0f 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -10,8 +10,6 @@ #define ACPIGEN_MAXLEN 0xfffff -#define CPPC_PACKAGE_NAME "GCPC" - #include <lib.h> #include <string.h> #include <acpi/acpigen.h> diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 463c16d..027a0e3 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -235,6 +235,8 @@ #define CPPC_VERSION_2 2 #define CPPC_VERSION_3 3 +#define CPPC_PACKAGE_NAME "GCPC" + /*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ enum cppc_fields { CPPC_HIGHEST_PERF, /* can be DWORD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc Gerrit-Change-Number: 59358 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel: Get cpu index based on LAPIC id
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59357 ) Change subject: cpu/intel: Get cpu index based on LAPIC id ...................................................................... cpu/intel: Get cpu index based on LAPIC id The patch adds a method to provide cpu index based on LAPCI Id. The function determines the cpu's LAPIC id and returns the position of the cpu's LAPIC id among the other cores' LAPIC ids. ` TEST=Verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If18116472aaa78cfa88350f313c246a28f67303d --- M src/cpu/x86/mp_init.c M src/include/cpu/x86/mp.h 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/59357/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c99732f..e8df692 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -207,6 +207,19 @@ park_this_cpu(NULL); } +uint32_t get_cpu_index(void) +{ + int i; + uint32_t cpu_index = 0; + uint32_t my_apic_id = lapicid(); + + for (i = 0; i < global_num_aps + 1; i++) + if (my_apic_id >= cpus_dev[i]->path.apic.apic_id) + cpu_index++; + + return cpu_index; +} + static void setup_default_sipi_vector_params(struct sipi_params *sp) { sp->gdt = (uintptr_t)&gdt; diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 7ed82dd..12241fc 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -146,4 +146,10 @@ /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +/* + * Returns cpu's index based on the position of the cpu's lapic id among other cpus' + * lapic ids. + */ +uint32_t get_cpu_index(void); + #endif /* _X86_MP_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If18116472aaa78cfa88350f313c246a28f67303d Gerrit-Change-Number: 59357 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add CPU related APIs
by Sridhar Siricilla (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Hello Nico Huber, Maulik V Vaghela, Sugnan Prabhu S, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59124 to look at the new patch set (#2). Change subject: soc/intel/common: Add CPU related APIs ...................................................................... soc/intel/common: Add CPU related APIs The patch defines below APIs : cpu_is_hybrid_supported() : Check whether CPU supports hybrid cores or not. cpu_get_bus_frequency() : Get CPU's bus frequency cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ration TEST=Verified on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I680f43952ab4abce6e342206688ad32814970a91 --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/59124/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680f43952ab4abce6e342206688ad32814970a91 Gerrit-Change-Number: 59124 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Angel Pons, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/../thermal: Use `clrsetbits32` API for setting LTT ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59310/comment/ea8d257c_e80da896 PS3, Line 67: ~ > because of integer promotion rules Aha, that makes sense! I just like the interface 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 16 Nov 2021 20:19:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shu...
by Tim Wawrzynczak (Code Review) 16 Nov '21

16 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59270 ) Change subject: mb/{adlrvp, brya, sm}: Set `pch_thermal_trip` for Dynamic Thermal Shutdown ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59270/comment/b64b2896_239ab510 PS4, Line 95: .pch_thermal_trip = 100, > > Isn't there usually a recommended value per-chipset? […] It would still be overrideable by any given mainboard in their overridetree or devicetree files too 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/59270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79 Gerrit-Change-Number: 59270 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 16 Nov 2021 20:18:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021