coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Revert "mb/google/brya/anahera: Disable autonomous GPIO power managem...
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Chen Wisley, Wisley Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58810 ) Change subject: Revert "mb/google/brya/anahera: Disable autonomous GPIO power management" ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: The CL fixing S0ix has landed, do you still want this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/58810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24aa5578aed35319b3613595433329e6aed31fe1 Gerrit-Change-Number: 58810 Gerrit-PatchSet: 2 Gerrit-Owner: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpatload: Implement new CBFS access API
by Julius Werner (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59497 ) Change subject: libpatload: Implement new CBFS access API ...................................................................... Patch Set 1: (17 comments) File payloads/libpayload/include/cbfs.h: https://review.coreboot.org/c/coreboot/+/59497/comment/ba08e7ee_14ddca40 PS1, Line 56: **********************************************************************************************/ I think it might be easier (for review and just generally keeping track of things) to just put all of this into separate files (e.g. this could go in a <cbfs_new.h> that is just chain-included from here, and then eventually when we remove the old stuff we rename that to <cbfs.h> -- or the other way round, move the old stuff to <cbfs_legacy.h> and chain-include it for now). https://review.coreboot.org/c/coreboot/+/59497/comment/5f83cf01_3c4c60ee PS1, Line 77: * cbfs_unmap() after it is done using the mapping to free up the memory, if possible. Rather than duplicate all this, maybe just refer to the coreboot header for documentation? https://review.coreboot.org/c/coreboot/+/59497/comment/bab4f2da_dd00f07c PS1, Line 79: * void cbfs_alloc(char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out): Loads We don't have that one here. https://review.coreboot.org/c/coreboot/+/59497/comment/c0e8a3cc_5159e2c0 PS1, Line 137: if (_cbfs_alloc(name, _cbfs_default_allocator, &arg, &size, force_ro, type)) Since we don't have cbfs_alloc() and we don't intend to implement more complicated allocators, I think this should all be simplified... e.g. you could have a common primitive like _cbfs_load(const char *name, void *buf, size_t *size_inout, bool force_ro), and when |buf| is NULL that just means it should malloc() a buffer instead. File payloads/libpayload/include/cbfs_core.h: https://review.coreboot.org/c/coreboot/+/59497/comment/5b8ad8e3_e05de37a PS1, Line 53: /* This function needs to be implemented to use _cbfs_alloc() based API */ What does this mean? This is all supposed to map back to libpayload_boot_device_read(), of course. File payloads/libpayload/libcbfs/cbfs.c: https://review.coreboot.org/c/coreboot/+/59497/comment/0985ae72_b1099799 PS1, Line 58: if (CONFIG(LP_NO_CBFS_MCACHE)) I'm not sure it's worth having a Kconfig here, I'd just say if the mcache exists in CBMEM it should use it, if not then not. https://review.coreboot.org/c/coreboot/+/59497/comment/6577f2bb_d63409e5 PS1, Line 65: (void *) Use phys_to_virt() whenever accessing pointers from lib_sysinfo (some payloads relocate themselves after parsing the coreboot tables, and set up virtual memory mappings). https://review.coreboot.org/c/coreboot/+/59497/comment/95c6545c_e48b296e PS1, Line 80: cbfs_get_boot_device(true); This was only needed for mcache building in coreboot, shouldn't apply here. https://review.coreboot.org/c/coreboot/+/59497/comment/dde18333_c22ad519 PS1, Line 83: cbfs_dev_size nit: a bit odd you wouldn't just use rw.dev.size here if you do it below https://review.coreboot.org/c/coreboot/+/59497/comment/54ee7b2b_cd787c9b PS1, Line 84: if (lib_sysinfo.cbfs_offset != 0 && lib_sysinfo.cbfs_size != 0) { This should never fail. If vboot is disabled in coreboot, these will just point to the RO CBFS. https://review.coreboot.org/c/coreboot/+/59497/comment/bc257348_4ee73568 PS1, Line 92: cbfs_boot_device_find_mcache(&rw, false); Shouldn't this be inside the !cbfs_dev_size() check (mcache would also be cached already if the rest is cached)? https://review.coreboot.org/c/coreboot/+/59497/comment/b7cef46c_739045d5 PS1, Line 96: cbfs_boot_device_find_mcache(&ro, false); Same here. There are specific reasons in coreboot for why it needs to try to regenerate the mcache again on every call (see the comment there), reasons which don't apply here. https://review.coreboot.org/c/coreboot/+/59497/comment/5f25e389_7c67156e PS1, Line 102: uint32_t size = 0; nit: Don't really need these, can just pass pointers &ro.dev.offset / &ro.dev.size directly. https://review.coreboot.org/c/coreboot/+/59497/comment/8ee6e146_784be9fd PS1, Line 105: die("Cannot locate primary CBFS"); This should probably be an error that's passed back up to the caller for libpayload, rather than die(). https://review.coreboot.org/c/coreboot/+/59497/comment/c63d99bd_604a3d68 PS1, Line 131: cbfs_err_t cbfs_walk(cbfs_dev_t dev, No, sorry, not like this. The point of commonlib/bsd/ was that all that code could be directly included/linked into libpayload, so that we no longer need to have all this awful duplication. Please change the libpayload Makefile so that directly inclusion/linking is possible (only for commonlib/bsd/, not for the rest of commonlib/). File payloads/libpayload/tests/libcbfs/Makefile.inc: PS1: license File payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c: PS1: Most of this test tests the code in commonlib/bsd/, so if we're reusing that I don't know if it's that useful to duplicate the whole test? I think you only need to test the aspects that aren't covered by coreboot's tests yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/59497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7 Gerrit-Change-Number: 59497 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 23:01:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Lance Zhao, Martin Roth, Tim Wawrzynczak. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Just curious.... […] This is the last one required for cezanne. -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 22:56:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/security/vboot/antirollback.h: https://review.coreboot.org/c/coreboot/+/59476/comment/d13baf47_54f14559 PS2, Line 39: SECURE_COUNTER1_NV_INDEX If you go this route, I would say put a comment saying that they are CR50 specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 22:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi,Makefile: Add preload_acpi_dsdt
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Lance Zhao, Raul Rangel, Martin Roth. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 ) Change subject: acpi,Makefile: Add preload_acpi_dsdt ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Just curious.... how many preload_blah() functions are going to be sprinkled throughout the code? -- To view, visit https://review.coreboot.org/c/coreboot/+/59504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Gerrit-Change-Number: 59504 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 22:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable secure counters
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59477 ) Change subject: soc/amd/cezanne: Enable secure counters ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/mainboard/google/guybrush/Kconfig: https://review.coreboot.org/c/coreboot/+/59477/comment/24d3f3bd_9a026e11 PS1, Line 57: VBOOT_STARTS_BEFORE_BOOTBLOCK > In theory we can do it. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6818c6f7905aa2eb815059e23c4f79437593f8ca Gerrit-Change-Number: 59477 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 19 Nov 2021 22:52:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57325 ) Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M ...................................................................... soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M This patch updates the VccIn Aux Imon IccMax for ADL-M Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I21753f2e5e9867f22c05e087cbf1f1e097d28bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/57325 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e43335e..e182089 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -43,6 +43,7 @@ #define ICC_MAX_ID_ADL_P_5_MA 32000 #define ICC_MAX_ID_ADL_P_6_MA 32000 #define ICC_MAX_ID_ADL_P_7_MA 32000 +#define ICC_MAX_ID_ADL_M_MA 12000 /* * ME End of Post configuration @@ -310,6 +311,9 @@ return ICC_MAX_ID_ADL_P_6_MA; case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: return ICC_MAX_ID_ADL_P_7_MA; + case PCI_DEVICE_ID_INTEL_ADL_M_ID_1: + case PCI_DEVICE_ID_INTEL_ADL_M_ID_2: + return ICC_MAX_ID_ADL_M_MA; default: printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", mch_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/57325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21753f2e5e9867f22c05e087cbf1f1e097d28bca Gerrit-Change-Number: 57325 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59411 ) Change subject: mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only ...................................................................... mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only If a USB_MUX_EVENT happens while the AP is in S3 during powerdown transtion (S0->S3->S5), this will cause the device to boot again after it has finished sequencing down to S5. Since S3 is not POR for ChromeOS devices anymore, change this event to wake from S3 and S0ix to just S0ix. BUG=b:206867635 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h index b346530..3c7fde5 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h @@ -43,10 +43,10 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS \ (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ -- To view, visit https://review.coreboot.org/c/coreboot/+/59411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301 Gerrit-Change-Number: 59411 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Add config option for S3 ACPI
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59024 ) Change subject: soc/intel/tigerlake: Add config option for S3 ACPI ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: > Wouldn't it make more sense to use a Kconfig option to enable/disable S0ix instead of a devicetree o […] Generally speaking yes, although IIRC we have had occasions in the past that required changing the value based on board revisions or silicon revisions -- To view, visit https://review.coreboot.org/c/coreboot/+/59024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Gerrit-Change-Number: 59024 Gerrit-PatchSet: 19 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 22:48:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/vboot: Set up secure counter space in TPM NVRAM
by Karthik Ramasubramanian (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Andrey Pronin, Raul Rangel, Paul Menzel, Julius Werner, Yu-Ping Wu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59476 ) Change subject: src/security/vboot: Set up secure counter space in TPM NVRAM ...................................................................... Patch Set 2: (1 comment) File src/security/vboot/secure_counter.h: https://review.coreboot.org/c/coreboot/+/59476/comment/40586765_55c27ab5 PS1, Line 14: SECURE_COUNTER4_NV_INDEX, /* 0x1012 */ > Done Sorry for prematurely saying done. I moved it to antirollback.h. Based on Raul's comment above, I feel it makes sense to define config items for: * Secure counter name * Secure counter starting NV Index * Number of consecutive Secure counters. This might help if more platforms use different secure counters for different purposes. Or do you think it is over-engineering? -- To view, visit https://review.coreboot.org/c/coreboot/+/59476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915fbdada60e242d911b748ad5dc28028de9b657 Gerrit-Change-Number: 59476 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 22:44:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021