coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/thermal: Allow thermal configuration over PMC
by EricR Lai (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/common/thermal: Allow thermal configuration over PMC ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/block/thermal/thermal_pmc.c: https://review.coreboot.org/c/coreboot/+/59209/comment/9a828d9f_38746aba PS13, Line 21: static uint8_t get_thermal_trip_temp(void) Would you mind make the get_thermal_trip_temp and pch_get_ltt_value in thermal_common.c? Of course you can do it in follow up CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 20 Nov 2021 05:56:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59310 ) Change subject: soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT ...................................................................... soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT This patch uses `clrsetbits32` helper function to set thermal device Low Temp Threshold (LTT) value. BUG=b:193774296 TEST=Able to build and boot hatch and adlrvp with this change. Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 1 insertion(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 4a2d8d8..6106c49 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -40,7 +40,6 @@ /* Enable thermal sensor power management */ void pch_thermal_configuration(void) { - uint16_t reg16; uintptr_t thermalbar; uintptr_t thermalbar_pm; const struct device *dev; @@ -65,9 +64,5 @@ thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - reg16 = read16((uint16_t *)thermalbar_pm); - reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; - /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(); - write16((uint16_t *)thermalbar_pm, reg16); + clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); } 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Gerrit-Change-Number: 59310 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/thermal: Hook up IA thermal block to romstage
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59391 ) Change subject: soc/intel/common/thermal: Hook up IA thermal block to romstage ...................................................................... soc/intel/common/thermal: Hook up IA thermal block to romstage This patch ensures IA common thermal block is now able to compile under romstage with necessary compilation issues fixed. BUG=b:193774296 Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59391 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/thermal/Makefile.inc M src/soc/intel/common/block/thermal/thermal.c 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc index 6f216b3..951065c 100644 --- a/src/soc/intel/common/block/thermal/Makefile.inc +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -1 +1,2 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index d6e401e..4a2d8d8 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -43,7 +43,7 @@ uint16_t reg16; uintptr_t thermalbar; uintptr_t thermalbar_pm; - struct device *dev; + const struct device *dev; struct resource *res; dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8 Gerrit-Change-Number: 59391 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/thermal: Drop unused parameter of pch_get_ltt_value()
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59390 ) Change subject: soc/intel/common/thermal: Drop unused parameter of pch_get_ltt_value() ...................................................................... soc/intel/common/thermal: Drop unused parameter of pch_get_ltt_value() `struct device *dev` as part of the pch_get_ltt_value() argument is being used hence, replace with `void`. BUG=b:193774296 Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59390 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 11a6108..d6e401e 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -23,7 +23,7 @@ } /* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(struct device *dev) +static uint32_t pch_get_ltt_value(void) { uint8_t thermal_config; @@ -68,6 +68,6 @@ reg16 = read16((uint16_t *)thermalbar_pm); reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(dev); + reg16 |= pch_get_ltt_value(); write16((uint16_t *)thermalbar_pm, reg16); } 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Gerrit-Change-Number: 59390 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/thermal: Allow thermal configuration over PMC
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Maulik V Vaghela, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/common/thermal: Allow thermal configuration over PMC ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: > thanks Subrata, this is a lot cleaner 😊 Thanks Tim 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 05:17:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow variants to choose CAR setup configuration
by Subrata Banik (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59272 ) Change subject: mb/google/brya: Allow variants to choose CAR setup configuration ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/59272/comment/b312d9fc_91f7e39d PS3, Line 134: BOARD_GOOGLE_BRYA0 > I am getting an ETA on decommission date for these older rev boards 👍 Thanks Tim, that would be good data to have -- To view, visit https://review.coreboot.org/c/coreboot/+/59272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe94e6b82739ec65829859271622d904d75e978d Gerrit-Change-Number: 59272 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 05:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/arch/ppc64/*: pass FDT address to payload
by Sergii Dmytruk (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Timothy Pearson, Ron Minnich. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57084 ) Change subject: src/arch/ppc64/*: pass FDT address to payload ...................................................................... Patch Set 14: (2 comments) Patchset: PS13: > Hmm wouldn't a linkerscript symbol shared in early stages, that you then move the cbmem in ramstage […] Thought handoff would be a more "correct" solution, but yeah it's just uglier. File src/arch/ppc64/fdt.h: https://review.coreboot.org/c/coreboot/+/57084/comment/00a106d6_96e65684 PS13, Line 9: CBMEM_ID_FDT_ADDRESS > CBMEM_ID are to be placed in commonlib/include/commonlib/cbmem_id. […] I thought it's too specific to the platform to put there. Moved. -- To view, visit https://review.coreboot.org/c/coreboot/+/57084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Gerrit-Change-Number: 57084 Gerrit-PatchSet: 14 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 00:35:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9: require hb-mode=on
by Sergii Dmytruk (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Paul Menzel, Arthur Heymans, Timothy Pearson, Ron Minnich. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57082 ) Change subject: src/mainboard/emulation/qemu-power9: require hb-mode=on ...................................................................... Patch Set 13: (1 comment) Patchset: PS12: > I'm pretty confused about all these symbols in ramstage. Most of these are in cbmem by that time. The conditional isn't there to remove unused symbols in ramstage, it's to take change in addressing into account. I've added a comment which should explain what's going on and resolve all of your comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/57082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Gerrit-Change-Number: 57082 Gerrit-PatchSet: 13 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 00:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
by Sergii Dmytruk (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Ron Minnich, Timothy Pearson. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57079 ) Change subject: src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard ...................................................................... Patch Set 12: (2 comments) File src/mainboard/emulation/qemu-power9/board.fmd: https://review.coreboot.org/c/coreboot/+/57079/comment/df376173_035e9cfa PS11, Line 12: FLASH@0 CONFIG_ROM_SIZE { : BIOS@0 CONFIG_ROM_SIZE { : BOOTBLOCK 128K : FMAP 0x200 : COREBOOT(CBFS) : } : } > This looks identical to util/cbfstool/default.fmd. […] Done File src/mainboard/emulation/qemu-power9/cbmem.c: https://review.coreboot.org/c/coreboot/+/57079/comment/b7f316bf_bf02a8cc PS11, Line 9: (1ULL << 32) - 1048576 > 4ULL * GiB - 1 * MiB Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Gerrit-Change-Number: 57079 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 00:34:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src/cpu/power9: add file structure for power9, implement SCOM access
by Sergii Dmytruk (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Felix Singer, Arthur Heymans, Krystian Hebel, Timothy Pearson, Ron Minnich. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57078 ) Change subject: src/cpu/power9: add file structure for power9, implement SCOM access ...................................................................... Patch Set 12: (1 comment) File src/include/cpu/power/scom.h: https://review.coreboot.org/c/coreboot/+/57078/comment/37ddbfd0_df4ba37f PS11, Line 91: static uint64_t read_scom_direct(uint64_t reg_address) : { : uint64_t val; : uint64_t hmer = 0; : do { : /* : * Clearing HMER on every SCOM access seems to slow down CCS up : * to a point where it starts hitting timeout on "less ideal" : * DIMMs for write centering. Clear it only if this do...while : * executes more than once. : */ : if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) : clear_hmer(); : : eieio(); : asm volatile( : "ldcix %0, %1, %2" : : "=r"(val) : : "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), : "r"(reg_address << 3)); : eieio(); : hmer = read_hmer(); : } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); : : if (hmer & SPR_HMER_XSCOM_STATUS) { : reset_scom_engine(); : /* : * All F's are returned in case of error, but code polls for a set bit : * after changes that can make such error appear (e.g. clock settings). : * Return 0 so caller won't have to test for all F's in that case. : */ : return 0; : } : return val; : } : : static void write_scom_direct(uint64_t reg_address, uint64_t data) : { : uint64_t hmer = 0; : do { : /* See comment in read_scom_direct() */ : if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) : clear_hmer(); : : eieio(); : asm volatile( : "stdcix %0, %1, %2":: : "r"(data), : "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), : "r"(reg_address << 3)); : eieio(); : hmer = read_hmer(); : } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); : : if (hmer & SPR_HMER_XSCOM_STATUS) : reset_scom_engine(); : } > None at this moment I guess. It started as just inlined `asm volatile(... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Gerrit-Change-Number: 57078 Gerrit-PatchSet: 12 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Nov 2021 00:33:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2021