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Hello build bot (Jenkins), Timothy Pearson, Ron Minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57084
to look at the new patch set (#16).
Change subject: src/arch/ppc64/*: pass FDT address to payload
......................................................................
src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed first to
romstage, then to ramstage, where it's put into CMBEM to be read on
starting payload.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/arch/ppc64/boot.c
M src/arch/ppc64/bootblock_crt0.S
M src/commonlib/include/commonlib/cbmem_id.h
M src/mainboard/emulation/qemu-power9/memlayout.ld
4 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/16
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Change subject: ec/starlabs: Add standardised ITE EC support
......................................................................
Patch Set 56:
(2 comments)
File src/ec/starlabs/merlin/Kconfig:
https://review.coreboot.org/c/coreboot/+/58343/comment/60ea8938_3d3e3aa3
PS55, Line 57: merin
> mer*l*in
Done
File src/ec/starlabs/merlin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58343/comment/42179438_756d6746
PS55, Line 9: CONFIG_EC_VARIANT_DIR
> shouldn't this be `EC_VARIANT_DIR`?
Done
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Change subject: cpu/intel/model_2065x: Use static.c exposed lapic 0
......................................................................
Patch Set 2: Code-Review+2
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Change subject: ec/starlabs: Add standardised ITE EC support
......................................................................
Patch Set 55: Code-Review+1
(2 comments)
File src/ec/starlabs/merlin/Kconfig:
https://review.coreboot.org/c/coreboot/+/58343/comment/dddd7b8d_bc6cb9a3
PS55, Line 57: merin
mer*l*in
File src/ec/starlabs/merlin/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/58343/comment/8dbd8b25_f7037b4a
PS55, Line 9: CONFIG_EC_VARIANT_DIR
shouldn't this be `EC_VARIANT_DIR`?
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Change subject: cpu/haswell/*.c: Use static.c exposed lapic 0
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59314/comment/474b8791_78f0aaa9
PS2, Line 7: cpu/haswell/*.c
How about `cpu/intel/haswell` instead?
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Change subject: util/sconfig: Expose apic devices
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59313/comment/e74503da_438f2af9
PS2, Line 10: needed in most cases.
Forgot to mention that the config of LAPIC 0 is also exposed.
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Change subject: cpu/haswell/*.c: Use static.c exposed lapic 0
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/auron/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/59314/comment/b4139667_6f0039de
PS2, Line 20: device lapic 0xacac off end
> There are different ways to set up the devicetree organizationally, and they're probably all going t […]
Out of curiosity, I've compared static.c of the Asrock B85M Pro4 before and after changing the following:
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index 43a65f8197..e73a24bfcb 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -1,15 +1,15 @@
+chip cpu/intel/haswell
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+end
+
chip northbridge/intel/haswell
# This mainboard has VGA
register "gpu_ddi_e_connected" = "1"
- device cpu_cluster 0 on
- chip cpu/intel/haswell
- device lapic 0 on end
- device lapic 0xacac off end
- end
- end
-
device domain 0 on
subsystemid 0x1849 0x0c00 inherit
The resulting static.c is nearly identical, only two lines change:
diff --git a/static.c b/static.c
index 4e0c4f4acb..6f149aff38 100644
--- a/static.c
+++ b/static.c
@@ -149,9 +149,9 @@ STORAGE struct device _dev_0 = {
.link_list = &_dev_0_links[0],
.sibling = &_dev_1,
#if !DEVTREE_EARLY
- .chip_ops = &northbridge_intel_haswell_ops,
+ .chip_ops = &cpu_intel_haswell_ops,
#endif
- .chip_info = &northbridge_intel_haswell_info_1,
+ .chip_info = &cpu_intel_haswell_info_1,
.next=&_dev_1,
#if !DEVTREE_EARLY
#if CONFIG(GENERATE_SMBIOS_TABLES)
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Change subject: cpu/intel/model_1067x: Use apic exposed in static.c directly
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> why treat this one differently?
This one has a socket, which supports multiple cpu's. It looks like only 1067x has a CPU chip config so it's probably possible to drop that magic LAPIC.
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Change subject: src/arch/ppc64/*: pass FDT address to payload
......................................................................
Patch Set 15:
(1 comment)
File src/arch/ppc64/boot.c:
https://review.coreboot.org/c/coreboot/+/57084/comment/60ba0859_0745b3c2
PS15, Line 43: /* Store FDT address to pass it to payload */
: entry = cbmem_entry_add(CBMEM_ID_FDT_ADDRESS, sizeof(_fdt_address));
: if (entry == NULL)
: die("Failed to add FDT address entry in CBMEM at romstage!");
:
: memcpy(cbmem_entry_start(entry), &_fdt_address, sizeof(_fdt_address))
arch_prog_run is not the right place to do this. Use ROMSTAGE_CBMEM_INIT_HOOK
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